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Low-power design animates panel in Taiwan

By Ron Wilson, Executive Editor -- EDN, 11/19/2007

A panel convened by Cadence Design Systems Inc. at a Fabless Semiconductor Association event in Taipei, Taiwan, earlier this month offered some useful insight into the state of low-power CMOS chip design, and some tips into where the real challenges lie in this increasingly mandatory phase of the SoC design process. Speakers addressed three questions: what are the fundamentals for a successful low-power design; what impact can designers expect to have on system energy consumption; and where are the major risks in low-power design compared to a conventional approach.

On the first question, fundamentals, Gagan Gupta, senior director of technology product marketing at IP vendor ARC International, pointed out that in addition to the obvious need for process, tools, and libraries that supported low-power design, a couple of less apparent factors are vital. One of these is use cases—detailed understanding of how the end-user system will be operated. He emphasized that unless chip designers understand how the final system will be used, they can’t know what to optimize and what to ignore. Second, Gupta emphasized the importance of software—not only because of its ability to waste more energy than hardware designers can possibly save, but also because of its increasing role in controlling hardware power-saving features such as clock scaling and power gating.

In contrast, CJ Hsieh, associate vice president at design services company Faraday Technology, focused on systems design and architecture. “The toughest job is establishing a plan early, and then synchronizing the efforts of different kinds of designers,” he said. “Power management requires global optimization, not a collection of local minima.”

Chi-Ping Hsu, corporate vice president at Cadence, began by warning that design teams could no longer expect power savings to come with a low power process by default. “The improvements from the process are at best incremental,” he said. Instead, Hsu emphasized the hard work all through the design process necessary to achieve adequate power savings. In particular, he spotlighted the problem of passing design intent about power management from each stage of the design flow to the next—and particularly in conveying the information into the verification process. “We have seen even the best teams have problems with verification on designs that use aggressive power management,” he warned. And Hsu underlined the role of Cadence’s Common Power Format in conveying power-management design intent between RTL designers, verification engineers and physical designers.

TSMC deputy director LC Lu supported Hsu’s warning about the difficulty of the undertaking and the need for it to be a program-wide effort. “Miss any major part of this process, and you can end up with higher power than if you’d done nothing, or worse, you can have a failed chip,” he said. Lu did challenge Hsu’s pessimism about the inherent power reduction of new processes, though. “You get a 30 percent reduction in power for free by moving to the new process.”

On the question of how much power designers could realistically expect to save at the system level, there was similar divergence of opinion. Gupta again emphasized use-models. He pointed out that static and dynamic power were separate issues addressed in different ways, and that use cases determined the relative importance of the two. A device that is only turned on when it is active—such as an MP3 player, must focus on dynamic power. But an always-on device with a low duty cycle, such as a cellular handset or network interface, must give more emphasis to static power. That said, he offered as an example that ARC had seen aggressive low-power design reduce overall energy consumption in their CPU core by 75 percent in some scenarios.

Hsieh added that hard work did not by itself guarantee good results. In more advanced processes, he said, leakage would come to dominate energy consumption even in devices with high duty cycles, simply because it was growing so rapidly with decreasing geometry—by a factor of four at each new node. Hsieh offered two examples: In an MP3 player, dynamic voltage scaling and some power gating achieved a 30 reduction in power. In a camera module that spent most of its time in standby, however, he said the design emphasis would be on reducing leakage by shutting off all power to some blocks.

TSMC’s Lu answered that he had seen designs that in moving to a new process node achieved twice the functionality in the same area and still reduced power compared to a previous design. But he warned that these savings didn’t come just from the process. Instead, they required aggressive design for low power. And techniques aggressive enough to do this were still in their formative stages. “Power-gating has become very popular, and big companies are using adaptive voltage scaling,” he said. “But when you get all the way to dynamic voltage-frequency scaling, timing closure becomes very difficult. We have only seen test chips using DVFS so far—no real designs yet.”

Addressing the question of new risks in low-power design, Gupta pointed to several difficulties. It is often very difficult, he said, for the chip design team to understand the way the end product will be used. Sometimes the system OEM isn’t willing to share that data, and sometimes the OEM simply doesn’t know. Additionally, Gupta said, it can become extremely complex for the chip verification team to verify the user functionality and the operation of the power-management features at the same time. Hsieh agreed that verification was a serious problem, pointing out two specifics. “In conventional flows, you never bother to simulate the power nets,” he said. “In aggressively power-managed designs, the power nets are active, and have to be simulated.” Also, he said, it was very difficult to maintain the integrity of power-management design data, even using the Common Power Format. “Having the same labels on power-gating signals in different blocks can lead to shutting down too many blocks, for instance,” he warned.

Hsieh went on to re-emphasize the need to verify wake-up and shut-down sequences, to ensure that the right level-shifter cells have been automatically inserted, and to verify other details of the power-management circuitry. In addition to verification, he concluded, test presents serious challenges. Design-for-test tools don’t necessarily create useful sequences for checking power-management functionality, and conventional test flows aren’t ready for it.

Cadence’s Hsu responded that at least his organization’s test automation tools handled power management structures properly, and suggested that perhaps Faraday was using someone else’s. But TSMC’s Lu quietly came to Hsieh’s defense on that issue, saying that there were still missing pieces in everyone’s approach to test generation for low-power designs. Nicely summarizing other panelists’ statements, Lu said that in addition to test, there were still serious problems that could arise as early as architectural design, during tool and IP selection, and in the choice of process. Mistakes or oversights in any of these areas, he warned, could lead to failure even with a highly skilled design team.