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Why design engineers need to know about lithography

This is the first of two articles that discusses the impact of lithography on a design engineer's work.

By Ann Steffora Mutschler, Senior Editor -- Electronic Business, 11/20/2007

In the 30-plus year history of semiconductor manufacturing, one of the biggest challenges has been to stay on track with Gordon Moore’s 1965 prediction, which calls for the doubling of the number of transistors on integrated circuits every two years.

To achieve this, feature sizes on those ICs have been made smaller, while chips have grown larger in size.

Looking just at feature sizes, the shrink is made possible in two ways: reducing the wavelength of the laser used to print the features onto the wafer, and adjusting the numerical aperture of the imaging tool to make the image print clearly on the wafer.

Accordingly, semiconductor manufacturers have moved to lasers with smaller wavelengths: from 436 nm in 1980, to 365 nm in 1988, to 350 nm in 1994, to 248 nm in 1998 and finally to 193 nm in 2001, where the industry remains currently.

However, the paradigm started to change with the 248-nm generation of lithography tools when people began patterning below the wavelength of the light source, explained Chris Bencher, distinguished technologist at Applied Materials. “When the pattern is smaller than the wavelength of the laser, image distortion can occur and the design is difficult to print. In addition, issues have been reported with images morphing in bizarre adjacencies,” he said.

In addition, the progression of smaller wavelengths has stalled. “We are stuck at 193 nm,” said lithography expert Chris Mack. “Lots of people are working on extreme ultraviolet [EUV] lithography [to extend the capabilities of 193 nm lithography]. At the present time, EUV is somewhere in the 5 to 15 year timeframe when it might possibly be ready, he added.  

Actually, Mack does not believe EUV will ever be ready -- because of the cost. “All decisions in lithography eventually come down to cost. The industry won’t be able to deliver the resolution at the proper cost. Even the most optimistic forecast puts EUV somewhere out close to more than five years away, which means we have a long way to push 193-nm lithography,” he explained.

In addition to the wavelength, the other factor in resolution is numerical aperture (NA) of the imaging tool. A popular method currently to increase the NA is immersion lithography which uses water.

To determine how difficult a design will be from a lithography standpoint, lithographers take the feature size they are trying to print and put it into the formula: wavelength/NA= k1, whereby k1 is a scaled resolution, and is a measure of how easy or difficult the lithography will be. If k1 is big, lithography is easy; if k1 is small, lithography is difficult. “Really hard” lithography translates to higher cost, Mack reminds. 

“We try to lower the wavelength to make k1 bigger and … in terms of increasing NA, immersion has enabled NA to be greater than one. But we’ve hit a wall with water immersion. There might be technologies developed over time, but many people wonder if it will work. So therefore, to improve resolution, we have to live with lower k1 [values],” he said.

“When it comes to the design world, as you go to lower k1 and litho gets harder, litho gets more sensitive to details of design. When k1 gets very small, some things are possible, some are not. So you have to start putting restrictions on design. We’ve always had design rules. Now, design rules are more complex and cumbersome, with designers getting increasingly frustrated to achieve good results,” Mack offered.

Applied’s Bencher believes maybe this year or next year we’ll see restrictions put on design. “When you look at ways to improve the wavelength of laser, there is no lower wavelength for the next 3 to 4 years. We are taking immersion lithography as far as we can go to increase the numerical aperture. Right now with 193 nm … this is pretty much it for the next 3 to 4 years. If you want to shrink feature sizes, you have to compromise on design.”

At the same time, Mack points out that design rules are fragile and don’t necessarily capture all the “know how” of the lithographers. “The paradigm of the design rule came about so that the design would work but the designer wouldn’t have to know about lithography. But these rules have stopped being easy to formulate and follow. So the whole paradigm has been breaking down very noticeably in the last five years,” he observed.

So what is there to do? “Make sure all the lithographers can build perfect design rule tables,” Mack suggested in jest. Will designers need to become litho experts and lithographers become design experts? Neither is realistic: Something else is needed.

“We don’t have an answer yet but the direction is through lithography simulation where lithographers pour their knowledge into tools that capture what they know and designers can access that data, to know what the ease or difficulty of the litho printability,” he said.

One of the main difficulties in developing these tools is timing, in the real world sense. “Designers need to be laying out standard cells and figuring out the place and route tools before the lithography process is ready to go for that process node,” Mack reminded. “If you are designing for a 3-year old TSMC process, for example, it will be difficult, but not impossible. For 32 nm, you have to start designing before the lithography is set. You have to know the litho process that is in store for you. There is much more uncertainty about what the litho process will be in two years,” he said.

This issue impacts the design cycle before manufacturing has begun.

In fact, according to a recent article in EDN, “with the introduction of 45-nm processing, foundries are now introducing restrictive-design rules (RDR) for bulk-CMOS processes, mandating the use of advanced low-power-design techniques, and requiring the use of design-for-manufacturing tools. Some foundries are also recommending that designers use probability-analysis tools, such as those for statistical-static-timing analysis and static statistical-power analysis to help reduce timing and power problems.”

Clearly, the day of the RDR has arrived.

There are other issues to be worked out as well in terms of simulation technology: How do you make sure you are simulating the right things? How do you make sure you have the correct input parameters that mimic the parameters you are trying to simulate?

The challenge to the lithography simulation OPC vendors is to understand how to move lithography information, which is used to drive simulation appropriately, upstream.

“There is a lot of talk about 'litho friendly design' but it hasn’t gained a lot of traction,” Bencher observed.

This is the first of two articles that discusses the impact of lithography on a design engineer's work. In part two, a third way to shrink feature sizes will be discussed: double –patterning techniques. As well, design tool suppliers chime in on their efforts in the area of lithography simulation.