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IBM, partners claim 32-nm high-k/metal gate SRAM, SOI

By Suzanne Deffree, Managing Editor, News -- Electronic News, 12/10/2007

Following on 45-nm high-k/metal gate work IBM promoted in January, the company and its joint development partners today announced a move to high-k/metal gate in 32-nm with SRAM and silicon-on-insulator (SOI) technologies.

As it has come to do more often in recent years, IBM relied on its various alliances to move to this next-generation process. The company credited AMD, Chartered Semiconductor Manufacturing Ltd., Freescale,  Infineon and Samsung in helping it make its move to 32-nm high-k/metal gate. IBM worked with Toshiba and Sony on its 45-nm advances; IBM said chips based on that work are manufacturing now.

“Once we got to 90-nm and gate oxide no longer could scale, we had to really change the model to a strong focus on materials and technology innovation to continue to move the technology forward. It’s just becoming more challenging with each technology node. By pooling the resources of the companies within this alliance, we are able to bring much more resources to bear on these challenges, as well as a very diverse group of skills and expertise in different market segments,” Gary Patton, VP of IBM's semiconductor research and development center, told Electronic News.

The 32-nm high-k/metal gate approach is based on a high-k gate-first process, and takes the stance that transistor-leakage and drive-current improvements should be made through metal gates and high-k dielectrics, opposed to other methods such as fully silicided silicon gates and stacked structures incorporating metal layers. While the debate on the best semiconductor materials for next-generation processes is still out, IBM and its partners claim that with the  high-k/metal gate material in the transistor they have been able to successfully shrink the size of a chip by up to 50 percent as compared to the 45-nm generation, while saving about 45% total power and allowing up to 30 percent higher performance in MPU applications in measurements performed at IBM’s East Fishkill, N.Y., 300-mm fab.

“This is not PowerPoint technology,” Patton said. “We have working SRAMs on both low-power bulk technology, as well as high-performance SOI technology at 32-nm and we have working SRAMs with cell sizes down below 0.15-sq. micron. I believe that is the smallest SRAMs ever reported with high-k/metal gate.”

The new approach to implementing high-k/metal gate will be available to IBM alliance members and their clients in the second half of 2009. IBM’s Patton said he expects 22-nm technologies in the second half of 2011, leveraging the Albany Nanotech Center for development and the East Fishkill IBM fab for production.

IBM will be providing further details on the technology at this week’s IEDM (International Electron Devices Meeting) in Washington, D.C.