ChipX combines standard cell, structured approach in Hybrid ASIC

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 12/18/2007

To allow for rapid and economical product line development, save companies an average of $300,000 to $500,000 in non-recurring engineering (NRE) and tooling costs and allow derivative products two to three months faster than today's methodologies allow, Santa Clara, Calif.-based mixed-signal ASIC provider ChipX Inc. today unveiled Hybrid ASIC, the implementation of a structured ASIC as IP on a standard cell device.

The company pointed out that an SoC developed in standard cell technology results in the smallest device size and best performance, but incurs significant up-front costs and long manufacturing lead times.

Also, producing a series of custom products becomes capital intensive and often prohibitive for many companies, whereas structured ASICs solve the problem of high up-front costs and long lead times but the level of integration is often limited to available platforms and sizes.

ChipX says its Hybrid ASIC gives developers the benefits of standard cell and structured ASICs without the tradeoffs, with turnaround time for logic changes as short as six weeks, from tape-out to packaged and tested prototypes with NREs starting as low as $99,000 in 0.13-micron.

Michelle Abraham, principal analyst for multimedia at market research firm In-Stat noted in a statement, “Designers of consumer multimedia products prefer to develop complete product families that give buyers a variety of choices. For example, one member of a video product line might have an H.264 CODEC only while another might add DivX. Consumer electronic manufacturers could greatly benefit from a fast, inexpensive ASIC methodology that enabled them to implement multiple products, and rapidly enter and dominate new market segments.”

The company also noted that Hybrid ASICs are meant to allow several generations of customized products or various derivatives to be built quickly and effectively.

Typical applications for Hybrid ASIC are expected to include video compression or data encryption on a single device with different compression or encryption schemes.

The Hybrid ASIC is also aimed at implementation of an ASIC with a pre-standard interface or algorithm, and in these cases, the potentially variable design logic is placed in the configurable structured ASIC area with proliferation of new products able to be quickly and easily built by changing just the design in this area, without requiring additional work on the fixed portions of the design.

Specifically, a Hybrid ASIC combines standard cell logic and I/Os, compiled memory and mixed-signal IP with a predefined configurable logic in a structured ASIC core and configurable memory.

The designer decides what functionality is built in the configurable portion of the chip and ChipX customizes a structured ASIC IP core in any shape (rectangle, L-Shape, etc.) or size (50,000 to 2 million gates) desired for the section of the design likely to be altered in the future.

Configurable memory blocks and configurable I/Os can also be inserted, offering various levels of flexibility and upgradeability.

With derivative products, only the changing portion of the design needs to be processed – reducing development time to a fraction of the initial development time -- typically tens or hundreds of thousand gates are processed instead of millions of gates, so that fabrication time can be reduced to a few layers of metal compared with 30 to 40 layers and the NRE cost reduced by 70 percent or more, the company said.

Hybrid ASIC products are customer specific and can contain up to 10 million ASIC gates and 10 Mb of memory.

ChipX also said it offers a range of IP, including PCI Express, USB 2.0 OTG, Video DAC and ADC, synthesizable processors from ARM, Beyond Semiconductor, DDR/DDR2 PHYs and controllers, as well as more than 200 blocks of synthesizable IP.

Finally, the company added that Hybrid ASIC designs follow industry-standard design flows and require only standard EDA tools, and is available in 0.13-micron CMOS process.