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Rethinking how to decrease power consumption
Rethinking power consumption from a system perspective can help lower power consumption, extend the life cycle of technology platforms, and lower the total cost of ownership of semiconductor products across the supply chain.
By Maurizio Skerlj, Staff Engineer, Qimonda AG -- EDN, 1/10/2008
For much of the history of the semiconductor industry, product roadmaps have been based on introducing higher performance, higher capacity, and higher speed devices, all of which translates into higher power consumption and, ultimately, higher cost, especially from a TCO (Total Cost of Ownership) perspective. In a mostly successful effort to minimize the ever-increasing consumption of power, the industry adopted new technologies and drove manufacturing processes to smaller geometries. However, the process treadmill may be reaching an end-point, and the use of in-creased parallelism and greater levels of integration may no longer be the best solution to optimizing power consumption. While relying on more advanced technologies reduce the size of chips and allow higher operating frequencies, the increased transistor densities and higher speeds of these devices can actually negate the power benefits of a process shrink and lead to a larger power consumption. It is time to re-think design to encompass the end-user point of view, reconsider architecture selection, and make power budgets a primary consideration at every stage of product creation.
Reducing a device's power consumption and the heat it generates were major motivators for the move from bipolar to CMOS processes, and CMOS is today facing the same dilemma. When the power density of a module approaches 12 W/cm2, it is not economically feasible to dissipate the heat. As Figure 1 shows, bipolar processes approached this level in about 1990, at which time CMOS was adopted as the mainstream process, effectively resetting the power clock. Today, CMOS is reaching the same point as bipolar was at in 1990 (Figure 1). CMOS geometry shrinks and voltage reductions have been used to minimize power consumption, but the immense quantity of smaller transistors that are now packed into a typical semiconductor device are being operated at higher frequencies and, even with lower voltages, are generating heat that is becoming harder to deal with. This presents a dilemma because there is not currently a viable alternative to CMOS.
A number of techniques, such as the use of copper and low-K dielectrics, offer a way to reduce heat generation by about 20 percent, but these require changes in fabrication equipment and so can be costly to implement. Even decreasing voltage is approaching the end of its usefulness as a power-saving method because 1.0 V, which is already being used in some applications, is proving to be a lower limit that is difficult to overcome in practical terms when both high-speed performance and good noise margins are desired. Because there is no clear successor to CMOS at hand, the industry needs to consider alternative approaches to reduce semiconductor device power consumption, including innovative use of architectures and paying particular attention to system-level issues to reduce power consumption while still meeting the increasing performance demands.
Architecture Selection
Considering the power budget, and its associated limitations, from the beginning of a project will change the rules of architecture selection. Designers need to consider power optimization as a key component of the initial system design rather than the traditional approach of creating a design for a product and then optimizing it. For example, if power is the first consideration, architectures using CML (current mode logic) and differential signaling techniques, which can support data rates above 10 Gbps but with a significant power penalty, must be carefully weighed against less-power-hungry techniques such as CMOS processes and single-ended architectures.
More careful consideration of architectures might allow technology evolution to proceed at a more reasonable level so that, rather than seeking to remain on the Moore's Law treadmill of doubling device density and speed/performance every 18 months or so (the actual pace changes over time and largely depends on the actual economic environment), the designer's focus can be on optimizing and prolonging the life of existing architectures by adding features to them. This concentration on architecture enhancement would result in more power-efficient, reliable products. For example, decreasing the operating voltage of DDR2 (second-generation double-data-rate) SDRAM to 1.5 V, which is 17 per-cent lower than the current standard, reduces power consumption and heat generation without any need to change the basic platform. In addition, extending the feature sets of existing architectures can have a significant, positive impact on the TCO across the entire supply chain. From the end-user point of view, systems with enhanced features are still new products, and can be introduced at whatever rate the manufacturer deems is correct for the market, while the OEM reaps the benefits of better control of the technology treadmill.
This is not to say, of course, that the process technology roadmap needs to be impeded. Rather, more efficient use can be made of each node. For example, memory suppliers, such as Qimonda, can create two variants for each process node, one for low-power, reasonable-performance devices and one for performance-oriented devices.
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From this perspective, a technology platform can be optimized to become the best it can be, lasting four to five years, rather than be made obsolete every two to three years. An example of this is the evolution of CellularRAM, a Pseudo SRAM (PSRAM) that mimics the SRAM and NOR Flash interfaces used for the XIP (execute-in-place) memory architectures that are common in voice-centric products. CellularRAM includes a logic circuit that automatically manages the refresh and precharge operations that are inherent to SDRAM technology. This relatively simple integration of SDRAM and logic created a new category of memory for mobile systems. It allowed manufacturers of legacy wireless platforms to extend the traditional six- to nine-month product life cycle of voice-centric phones by making minor system modifications to accommodate CellularRAM, achieving increased performance and density compared to SRAM, with lower standby and operating currents than traditional SDRAM.
| SDR SDRAM | DDR SDRAM | DDR2 SDRAM | DDR3 SDRAM | Units | |
| Year of Introduction (BEOL) | 1997 | 2000 | 2004 | 2007* | |
| Data Rate | 66, 100, 133 | 200, 266, 333, 400 | 400, 533, 667, 800 | 800, 1066, 1333, 1600 | Mbps per pin |
| Clock Frequency | 66, 100, 133 | 100, 133, 166, 200 | 200, 266, 333, 400 | 400, 533, 667,800 | MHz |
| I/O Power Supply | 3.3 (+/- 0.3) | 2.5 (+/- 0.2) | 1.8 (+/- 0.1) | 1.5 (+/- 0.075) | V |
| Burst Length | 1, 2, 4, 8 | 2, 4, 8 | 4, 8 | 8 (chop 4) | Bit |
| CAS Latency | (1), 2, 3 | (1.5), 2, 2.5, (3) | (2), 3, 4, 5 | 5, 6, 7, 8, 9, 10, (11) | Clock |
| Additive Latency | - | - | 0, 1, 2, 3, 4 | 0, CL-1, CL-2 | Clock |
| Write Latency | 0 | 1 | RL-1 | 5, 6, 7, 8 + AL | Clock |
Similarly, DDR2 SDRAM began as an extension of DDR, with the expectation that it would rapidly be replaced by DDR3. However, enhancements to DDR2 have achieved performance improvements that allow it to be used in applications otherwise calling for lower-end DDR3, which requires a new memory controller and therefore might be more costly to use Table 1). The additional capabilities will lengthen the DDR2 market life before the move to the next-generation architecture becomes necessary, and additional variants of DDR2 SDRAM, built on the mainstream plat-form, will continue to extend its useful life (Table 2).
| LP (Low-Power) DDR2 | DDR2 "1v5" | DDR2-1066 | Units | |
| Data rate | 800, (1066) | 400, 533, 667, (800) | 400, 533, 667, 800, 1066 | Mbps per pin |
| Clock frequency | 400 (533) | 200, 266, 333, (400) | 200, 266, 333, 400, 533 | MHz |
| I/O Power Supply | 1.2 (±0.8) | 1.50 - 1.90 (1.55 nom) | 1.8 (+/- 0.1) | V |
| Burst Length | 4, 8, 16 | Same as DDR2 | Same as DDR2 | Bit |
| Read Latency (CAS Latency) | 3, 4, 5, 6, 7, 8 | Same as DDR2 | Same as DDR2 | Clock |
| Additive Latency | TBD | Same as DDR2 | Same as DDR2 | Clock |
| Write Latency | TBD | Same as DDR2 | Same as DDR2 | Clock |
| Main Benefit | Almost one order of magnitude reduction of current consumption in Idd2p, Idd3p, Idd6 | About 20 - 30% power saving in all conditions | 33% speed increase |
Until recently, mobile phones, portable computers and other battery-powered systems were the only products in which power budgets were an early design consideration. But evolution of the system market, and increasing energy costs, have made such power budget considerations an important factor for virtually all systems. Today's desktop computers still demand high performance, particularly for graphics applications, and must also meet "green" requirements. In home entertainment systems, operation must be noise-free, which means no constantly running and annoying cool-ing fans, so low power consumption and low heat dissipation are a must.
In the server world, the overall power bill of a server farm is now a primary consideration. The density that can be achieved in a server farm is a function of how many devices can be integrated into it -- how much power per square foot it consumes. The cooling of the chips impacts reliability, and adds to the power bill, beyond what the devices themselves consume. For example, server farms use almost ten times the energy per square foot as office space, and server power alone may cost more than $75 million a year. Moreover, to control heat-related issues, a typical data center may consume 100 watts of cooling power for every 100 watts used to power a server, which is a large cost multiplier just to keep the equipment cool.
Memory Subsystems
One of the major energy consumers in computing and communication systems is the memory subsystem. For example, in laptops and PCs, the processor has the largest impact on the total power consumption, with the memory subsystem contribution being about 10 percent. For a mobile phone, the power demands of memory, at 20 percent of the total budget, are equal to the demands of the application processor. In a server, the memory subsystem may represent from 10 to 25 percent of the power consumption; on a blade server unit, for example, the memory subsystem contributes as much as 15 percent to power usage. This typically represents the second-largest power drain in the system, after the processors.
Although each of these systems has radically different performance and power requirements, they all use basically the same SDRAM. Specialized SDRAMs have been developed, such as graphics SDRAM for performance-hungry systems and CellularRAM and Mobile-RAM for mobile systems, but they rely on the same basic SDRAM technology. Historically, the dominance of mainstream SDRAM architectures has been a product of low cost, which is a result of enormous economies of scale in production of the commodity. It is up to a system designer to make the power-versus-performance tradeoff to determine which of the choices is correct for a particular application and power budget.
The FB-DIMMs (Fully Buffered Dual-in-Line Memory Modules) that are in wide use today, especially in server applications, combine relatively small SDRAM devices with an AMB (Advanced Memory Buffer) in a single module that has a serial, rather than parallel, architecture. When a single supplier produces the SDRAMs, the AMBs, and the modules, the communications channel between the memory and buffer can be optimized and the overall power con-sumption of the FB-DIMM minimized by careful design. This proven FB-DIMM architecture is now being enhanced by use of DDR2 SDRAMs and AMBs operating at 1.5 V, which has been shown to decrease power consumption by as much as 20 percent. This solution is particularly appealing because it does not require any special support from the CPU or the chipset, allowing every OEM or mother-board designer to take immediate advantage of it. In addition, the single-ended communications protocol used in DDRx (ranging form DDR to DDR3) can be extended up to 5 Gbps, consuming less power than the differential signaling-based protocol that is otherwise expected to be required to get to such higher data rates.
To meet increasingly stringent power requirements, it is no longer sufficient to pursue the latest generation of high-speed chips. It is now necessary that a power consumption envelope characterized with realistic workload assumptions, encompassing both stand-by and operating conditions, be determined at the beginning of the system definition process. The power envelope can then be used to judge the power consumption of each feature to create a sustainable product roadmap. Decisions as to which architecture will optimize power usage can then be made, whether that means moving to an advanced architecture or relying on a proven one with suitable extensions and enhancements.
