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Reducing buck converter input capacitance through multi-phasing and clock synchronization

The input capacitor of a buck converter is a critical power train component. This article provides an examination of the input capacitor requirement for single- and multiple-channel buck converter voltage regulators.

By T. Hegarty, Applications Engineer, Low Voltage Power Management, National Semiconductor, Tucson AZ -- EDN, 1/28/2008

This article provides an examination of the input capacitor requirement for single- and multiple-channel buck converter voltage regulators. The input capacitor of a buck converter is a critical power train component given its ripple current handling requirement and an input bus ripple voltage specification. Thus, the derivation of the input capacitor rms current is considered. By examining the input capacitor current waveforms of a two channel buck converter, the effects of ripple current cancellation are readily apparent and six distinct modes are evident depending on duty cycle magnitude of each channel.

The article also validates the advantages associated with operating multiple converters out of phase from one another. Due to multi-phase interleaving, the input capacitor rms current is reduced and the required capacitor size for a given input ripple voltage requirement is smaller. This is important given that the input filter capacitor requirement can be quite large for a conventional buck topology as it provides the switched AC current to the high side switch. Exemplarily, the theoretical advantages of interleaving are validated by results obtained from an experimental two-phase buck converter design.

The power train schematic diagram of a typical buck converter with output voltage V_o and output current I_o is shown in Figure 1. Ideal components are shown with parasitics such as switch on-resistance, inductor DCR and capacitor ESR and ESL not represented. The high side switch, S₁, is driven for time duration t_on with duty cycle ratio D given by

                                                                     (1)


The low side switch, S₂, is driven complementarily with duty 1–D. Both switches operate at constant switching frequency f_s = 1/T_s, where T_s is the switching period. The output filter consists of inductor L_f and capacitor C_f. The input filter capacitance is denoted by C_in. The input and output capacitor currents are i_Cin(t) and i_Cout(t), respectively, with polarity as indicated. The buck stage current waveforms are also indicated in Figure 1.

Neglecting power losses, the average DC input current is given by

                                                                    (2)

It is assumed that the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitor. Neglecting inductor ripple current, the input capacitor sources current of amplitude I_o-I_in during the D interval as S₁ conducts. Conversely, the capacitor is charged by I_in during the 1-D interval when S₂ conducts. With the current polarity as indicated, this can be written as

                                                          (3)


Thus, the input capacitor conducts a square-wave current of peak-to-peak amplitude I_o and it follows that the resultant capacitive component of AC ripple voltage is a triangular waveform with peak-to-peak amplitude specified by equation (4). The maximum ripple voltage occurs at 50% duty cycle and is equal to I_o/4f_sC_in.

                                                         (4)

Evaluating charge balance on the input capacitor yields

                                                                     (5)

This reduces to equation (2) above. If ∆i_L is the peak-to-peak inductor ripple current given by

                                                        (6)

then the input capacitor rms current, I_Cin,rms, is calculated as follows

                                                (7)


Substituting (2) into (7) and solving gives

                                                                 (8)

The input capacitor component selection process can proceed knowing this rms current result, the required capacitor DC voltage rating, and the maximum ambient temperature specification.

Figure 2 shows a plot of I_Cin,rms versus duty cycle. The vertical axis is normalized with respect to I_o. In general, the filter inductor is selected such that ∆i_L~0.3I_o and the ∆i_L term in equation (8) becomes negligible. Hence, I_Cin,rms reaches a maximum of approximately I_o/2 at 50% duty cycle.

Figure 3 shows the power train schematic of a typical dual channel buck converter with parallel connected input and dual independent output voltages, V_o1 and V_o2, and output currents, I_o1 and I_o2, respectively. The oscillators are synchronized with 180° phase difference to achieve interleaved PWM switching. The channels are controlled with arbitrary duty cycles D₁ and D₂ at constant frequency f_s given by equation (9).

                                                               (9)

An example of the practical implementation of this topological architecture is the National Semiconductor LM26400^[1] wide input range, dual output, asynchronous buck regulator with integrated high side FETs, peak current mode control and internal compensation network. Alternatively, the National Semiconductor LM201xx^[2,3] is a monolithic, current mode, full featured synchronous switcher family that boasts a sync-in/sync-out feature to facilitate bi-phase operation consistent with the schematic in Figure 3. Related products in the National Semiconductor product portfolio include LM5642 and LM2717 dual buck regulators^[4-5] and LM2657, LM2633, LM2645 and LM2648 synchronous buck controllers^[6-9].

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By considering the generalized input filter capacitor current waveform of a two channel buck converter, the rms current expressions for the capacitor can be derived. Indeed, there are six cases related to the operating points of duty cycles D₁ and D₂. If either duty cycle exceeds 50%, the individual input currents overlap. The fundamental ripple frequency is 2f_s and the resultant ripple voltage amplitude will be significantly lower than that of an equivalent non-interleaved buck stage.

1.        D₁, D₂ ≤ 0.5

Consider the input capacitor current waveform illustrated in Figure 4 for a two channel buck operating with duty cycles D₁ and D₂ less than 0.5 and output currents I_o1 and I_o2, respectively. Positive current is again defined as flowing into the positive input capacitor terminal. The currents related to channels 1 and 2 are colored red and blue respectively.

It is apparent that the total average input current is the sum of the individual average input currents given by

                                                                (10)

The input capacitor current, neglecting inductor ripple current, during the D₁ and D₂ intervals is I_o1−I_in and I_o2−I_in, respectively. The capacitor is charged by I_in for the remainder of the switching period, (1−D₁−D₂)T_s.

                                             (11)


The input capacitor charge balance yields

                                                       (12)

This reduces to the expression for average input current, equation (10) above. The input capacitor rms current is described by equation (13).

                                            (13)



Substituting (10) into (13) and simplifying produces the result of equation (14).

                                (14)

2.       D₁, D₂ > 0.5

Similarly, when duty cycles D₁ and D₂ are both greater than 0.5, the input capacitor current components from the two channels are shown in Figure 5(a) and given by

                                 (15)

The cumulative of these components yields the actual input capacitor current as presented in Figure 5(b). The rms current is

                                         (16)

Substituting (10) and simplifying gives the solution expressed by equation (17).

                                          (17)

If D₁=D₂=0.5, then equations (14) and (17) predict the same result, specifically I_Cin,rms = 0.5(I_o1 – I_o2). Thus, the input capacitor rms current is zero if the duty cycles are both 50% and the output currents are equal. As before, the fundamental ripple frequency is 2fs and the accrued benefit related to ripple current cancellation is lower input capacitance requirement.

The generalized case has four additional operating conditions to consider. Two cases correspond to when D₁ is less than 0.5, D₂ is greater than 0.5, and (D₂-0.5) is greater or less than D₁. The other two cases are the corollary where D₂ is less than 0.5, D₁ is greater than 0.5, and (D₁-0.5) is greater or less than D_2.

3.       D₁ ≤ 0.5, D₂ > 0.5, (D₂-0.5) < D₁

4.       D₁ ≤ 0.5, D₂ > 0.5, (D₂-0.5) ≥ D₁

The applicable current waveforms are depicted in Figure 6 and Figure 7. The input capacitor current components, rms current calculation and solution by substitution of (10) are provided with respect to cases 3 and 4 by expressions (18) and (19), respectively.

                                      (18)


                                      (19)


5.       D₁ > 0.5, D₂ ≤ 0.5, (D₁-0.5) < D₂

6.       D₁ > 0.5, D₂ ≤ 0.5, (D₁-0.5) ≥ D₂

The result for conditions 5 and 6 can be obtained by interchanging D₁ and D₂ in equations (18) and (19). The complete representation of I_Cin,rms that considers all duty cycle scenarios referenced above is presented in equation (20).

 (20)

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Usually, the converter output voltages are fixed and the input voltage is variable over a certain range. Thus, if the parameter defined as y=D₂/D₁=V_o2/V_o1 is constant^[6], then, by differentiation, the worst case rms input capacitor current occurs at

                                    (21)

A few iterations may be required before the worst case duty cycle and hence input voltage operating point is derived. It is also of merit to calculate the result with one channel at no load and the other at full load using equation (8).

Figure 8 shows a 3D plot of I_Cin,rms with D₁ and D₂ as variables assuming each channel is equally loaded and the total output current is 1A, i.e. the per phase current is 0.5A. Note the function minimum at D₁=D₂=0.5. Also evident is the higher rms current represented by the red tinted areas in Figure 8 that coincide with a line defined by . Peak rms current occurs at duty cycle pairs {D₁,D₂}={0.25,0.75} and {D₁,D₂}={0.75,0.25} such that

                                                            (22)






Alternatively, Figure 9 shows a 3D plot with duty cycles D₁ and D₂ defined as fixed values 0.45 and 0.70, respectively. The output currents at I_o1 and I_o2 are each varied from 0A to 0.5A. Again, note the result at I_o1 = I_o2 where the benefits of ripple current cancellation are maximized. Also evident is high rms current when one channel is fully loaded and the other is at no load. This is essentially the same result as that expected with a single-phase buck converter.

Taking this analysis a step further, consider the case where the outputs are connected together as shown in Figure 10 such that D₁=D₂=D. Assuming ideal current sharing due to interleaving so that I_o1=I_o2=0.5I_o and given synchronized clocks with 180° phase difference, then equations (14) and (17) can be expressed as illustrated by (23).

                                                    (23)

If the inductor ripple currents are equal, then equation (24) can be derived. However, the extra term due to ∆i_L is usually insignificant if standard inductor selection criteria are employed.

                                   (24)


An interleaved multi-phase buck converter implementation with N phases is illustrated in Figure 11. The oscillators are synchronized such that the phase shift between adjacent phases is 360°/N. Such multi-phase interleaved circuits are the sine qua non in VRM/VRD type computing and server applications where large output current and fast transient response within tight output voltage specifications are mandatory requirements.

The switches are shown implemented using n-channel high side and low side MOSFETs, denoted by Q_T1, Q_T2,..., Q_TN and Q_B1, Q_B2,..., Q_BN, respectively. By symmetry, L_f1 = L_f2 = … = L_fN. In general, the duty cycles and output currents of each stage are equal as given by (25). The average input current is the sum of the individual phase average input currents.

                                                           (25)


The fundamental ripple frequency at the input and output is Nf_s. In this instance, the input capacitor rms current can be written succinctly by equation (26) where m = floor﴾N·D) and the floor function returns the greatest integer value less than the argument.

                                                       (26)

Figure 12 shows a plot of normalized input capacitor rms current for two up to five interleaved phases. The result is normalized to I_o = 1A. TheI_Cin,rms minima appear at critical duty cycles given by equation (27).

                                                     (27)




Note that, in practice, the rms minima will not be quite at zero due to a residual rms component attributed to inductor ripple current. TheI_Cin,rms peaks occur at duty cycles given by (28). In general, I_Cin,rms will be at a minimum or maximum if the sum of the duty cycles equals 1.0 or 0.5, respectively.

                                                       (28)

If the duty cycle is known for a certain application or where there is little expected input voltage variation, then it is possible to choose N with reference to equation (27) such that the input capacitor rms current is substantially eliminated. Accordingly, a high current multiphase buck regulator can be defined with dramatically reduced input capacitor related cost, size, profile and PCB area. Furthermore, power dissipation in the ESR is reduced which reduces capacitor self-heating and extends capacitor lifetime. Lastly, high current slew rates and any correlated EMI are minimized and, given the higher fundamental ripple frequency, an EMI filter is smaller and less expensive to realize.

The benefits of interleaving were evaluated experimentally by designing a PCB to incorporate National Semiconductor LM20134^[2] and LM20154^[3] current mode, synchronous, 4A buck regulator ICs. The LM20134 and LM20154 are provided with sync-in and sync-out synchronization^[2,3] features, respectively. The interleaved configuration, deployed according to the schematic diagram in Figure 13, is capable of providing a net output current of 8A.

The LM20134 sync-in and the LM20154 sync-out pins are connected. Thus, the LM20154 acts a master providing a synchronization pulse that compels the LM20134 slave to operate with 180° phase difference. A 1MHz switching frequency is governed by free-running clock frequency of the LM20154.

Figure 14 shows the measured individual inductor currents and the total unfiltered output current with circuit operating conditions set at V_in = 4.5V, V_o = 1.8V and I_o = 8A. The currents are measured using Tektronix TCP202 50MHz current probes. With duty cycle at 45%, the ripple current cancellation and double frequency 2MHz ripple component are readily observed. 

Figure 15 shows the input capacitor current given the same circuit operating conditions. The measurement is obtained using a current sense (CS) transformer with low leakage inductance to minimize insertion impedance. The CS transformer turns ratio is 50:1 and the burden resistor is 5W. The same measurement is made when two LM20154 regulator ICs are operating in phase. As expected, there is a substantially lower ripple current present with the interleaved case relative to in-phase operation.

The article discusses the advantages associated with operating multiple converters out of phase from one another. Given multi-phase interleaving in a buck converter, the input rms current is dramatically reduced, the effective frequency is scaled higher, and the required input capacitor is smaller. The relevant input capacitor rms current equations are derived for an arbitrary two channel interleaved buck converter power stage. An experimental prototype of a two-phase buck regulator with synchronization capability is employed to confirm the advantages of interleaving.

[1] National Semiconductor, LM26400Y Dual 2A, 500kHz Wide Input Range Buck Regulator Datasheet, http://www.national.com/pf/LM/LM26400Y.html

[2] National Semiconductor, LM20134 Datasheet, http://www.national.com/pf/LM/LM20134.html

[3] National Semiconductor, LM20154 Datasheet, http://www.national.com/pf/LM/LM20154.html

[4] National Semiconductor, LM5642 Dual Synchronous Buck Regulator Datasheet, http://www.national.com/pf/LM/LM5642.html

[5] National Semiconductor, LM2717-ADJ Dual Step-Down DC/DC Converter Datasheet, http://www.national.com/pf/LM/LM2717-ADJ.html

[6] National Semiconductor, LM2657 Dual Synchronous Buck Controller Datasheet, http://www.national.com/pf/LM/LM2657.html

[7] National Semiconductor, LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs Datasheet, http://www.national.com/pf/LM/LM2633.html

[8] National Semiconductor, LM2645 Advanced Two-Phase Switching Controller with Two Linear Outputs Datasheet, http://www.national.com/pf/LM/LM2645.html

[9] National Semiconductor, LM2648 Two-Phase, Synchronous Step-Down 3-Channel Switching Regulator Controller Datasheet, http://www.national.com/pf/LM/LM2648.html