News and New Products

Magma makes DRC incremental with Talus QDRC, plans transistor level extractor

Magma Design Automation wants to proactively place and route ICs that are DRC-clean with the introduction of its new tool, Talus QDRC. In addition to Talus QDRC, the company also let slip that has a new transistor level extraction engine in the works.

By Michael Santarini, Senior Editor -- EDN, 1/31/2008

Magma Design Automation wants to help users reduce overall design rule checking (DRC) time by running design rule checks incrementally during place and route with its new tool, Talus QDRC.

Traditionally, designers run DRC after detailed routing to make sure none of the targeted foundries’ processes rules are violated. Inevitably, they’ll find several mistakes and have to transfer GDSII files back to place and route tools to fix them. And after they implement those fixes, they often introduce new violations, so the process needs to be repeated several times.

The process is made extremely painful by the fact that streaming the GDSII files between tools can take several hours, even days. A typical design with 10 million instances turns into GDSII file that is around 8 GB in size.

Magma hopes to relieve some of that pain and speed up the process with Talus QDRC. Kevin Walsh, senior vice president of marketing for Magma's physical verification business unit, said that Talus QDRC is essentially an integrated DRC within the implementation flow operating on Magma’s Unified Data Model.  “The major advantage is that you can now do these DRC checks on the implementation database and eliminate the need to stream GDSII out into DRC tools like Calibre, Hercules or even Quartz and make the changes,” said Walsh.

According to Walsh, design sizes are getting so large that if you have to steam out design files it affects data integrity, and you pay the cost of the stream out time, the edit marker, and the time it takes to correct a violation so you can move onto the next step in the flow.

Walsh noted that some DRC violations occur early in the implementation process, while others occur later in the design process. QDRC allows users to do some design rule checks at the point in flow where they are most likely to occur, which saves stream time, analysis time and fixing time at signoff DRC. “Because it’s operating on Magma’s memory resident data model, we can do a true incremental DRC,” said Walsh.

Other vendors claim to also have incremental DRC tools, but Walsh said that competing tools are not truly incremental because their tools stream out large GDSII files, then generate reports on different parts of the design so users can get to work on those problems. “We are actually truly incremental on the data model, so the changes you make are immediately reflected back on the design,” said Walsh.

After designers do placement and IP insertion for example, they can run QDRC to do IO pad ring checks, block placement, and power grid mesh integrity checks. Then after they run detailed routing, they can do broad-base geometry effects including antenna rules, pin issues, and IP inconsistencies. At the chip finishing stage they can then run checks for metal insertion, decoupling caps, and manufacturability aspects. Then during post route optimization, they can run incremental DRC checks for engineering change orders and DFM. The final GDSII files can then be run through signoff DRC. Walsh noted it can be Magma’s Quartz DRC tool or even Mentor’s Calibre.

Talus QDRC isn’t an interactive DRC tool like vendors offer in the analog and mixed-signal space. Those interactive tools allow users to draw parts of the circuit, then the tool comes back immediately and tells them whether or not the feature they just drew introduced a DRC violation.

Walsh noted that an interactive tool is not practical for an ASIC flow, but certain features of those tools are captured in QDRC. For example, Walsh said that QDRC notes whatever the placer or the router has changed and then it DRCs only runs the changed parts of the design. “It allows you to preserve data integrity and efficiency of the operation,” said Walsh. “What used to take days can be completed in hours.”

Magma claims using the tool in SoC flows will allow users to cut overall DRC time from eight days to roughly 20 hours. Magma claims performance is linearly scalable and can be run in a small memory footprint so bigger files run fast, too.

Walsh said that customers can use the Talus QDRC with DRC tools. They can, for example, call the rules deck for Mentor’s Calibre DRC tool. But the company has extra features that encourage users to use a full Magma flow. “We have an auto routing run set generation capability that basically looks at the technology files of a foundry and does a first level rules deck construction,” said Walsh. “What we’ve done with TalusQDRC, we’ve built that into an automatic run set generator that allows them to bring in IP and make sure those routes are DRC clean at the first level.”

In addition to Talus QDRC, the company also let slip that has a new transistor level extraction engine in the works. The company is not releasing any details of the product, but Walsh said that it will be looking at among other things strain silicon effects. “We expect at 32 nm, there will be different transistor structures, so this is a product that is targeting some of the new flows,” said Walsh.

Talus QDRC’s pricing will vary depending on the bundling customers purchase, but the tool runs standalone in the $40,000 to $60,000 range.