Where’s the ROI in DFM?

DesignCon panelists say the answer to the question “Where's the ROI in DFM?” depends largely on what process node you are tackling.

By Michael Santarini, Senior Editor -- EDN, 2/13/2008

To most designers the answer to the question “Where is the ROI in DFM?”  remains somewhat illusive. But panelists at last week’s DesignCon 2008 said that as more designs move to advanced processes, the return on DFM investment will become evident as DFM will become mandatory.

Panelists included Luigi Capodieci, fellow, RET/OPC automation and DFM at Advanced Micro Devices; Nitin Deo, senior director of DFM marketing at Cadence; Ross Hirschi, director of DFM at Freescale Semiconductor; Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks; and Edward Wan, senior director of design services marketing at TSMC North America.

Today the bulk of digital ASICs and SoCs are being designed at the 90-nm node. At that fairly mature process geometry, some DFM tools such as OPC (optical proximity correction) and PSM (phase shift mask) tools are required to make sure designs yield well. Those types of tools are traditionally used by designers in charge of the very end of the design process—those who do chip finishing or mask data preparation.

But panelists said as designs move to 65 nm, designers will need to use more DFM tools earlier in the design process and the learning curve gets a bit steeper as some designers will have to start using model based DRC and lithography simulation. Panelists said DFM is strongly recommended at 65 nm, but may not be needed. They said, however, at 45 nm, DFM tools become mandatory.

“I appreciate that the bulk of the industry is still at 90 nm,” said AMD’s Capodieci. “But when you get to 32 nm, let me tell you it’s not a question of ‘do you DFM or don’t you,’ it’s ‘tell me anything you can to help make my designs manufacturable.’ Period. That’s the future.”

Thus, panelists said the answer to the question “where’s the ROI in DFM?” depends largely on what process node you are tackling. But even the most advanced users say that while DFM ranges from useful to mandatory, it is still hard to quantify DFM’s ROI.

Capodieci said his company has been using DFM for many years but cannot quantify its impact. “We are using it well beyond 45 nm,” said Capodieci. “We are using at 32 and 22 nm for the development. The key benefit of it is that DFM allows for the codevelopment of design and technology at the same time. That’s the great return on investment. In the old style there was always a skew, as the technology had to be ready for designs. Now we are doing [design and manufacturing] at the same time because we have this interchange between technology and design that is mediated by DFM.”

Freescale’s Ross said that a few years ago, the company created a group to focus on DFM. The group consists of experts from both design and manufacturing disciplines. And because Freescale has multiple design projects going on at any given time targeting different process nodes, the DFM group prescribes various levels of DFM to each group, offering training and advice on tools and techniques.

“At 90 nm we have a couple of things we suggest: OPC, RET, tiling,” said Ross. “When you talk about model based lithography and CMP simulation and SSTA, we don’t see those as applicable at 90 nm. We see those applicable starting at 65 nm and mostly at 45 nm. It’s better to be safe than sorry or an ounce of prevention is worth a pound of cure. We make sure that any technique we apply, we do not allow it to increase the die size.”

Hirschi said the group can’t quantify Freescale’s return on in investment in DFM but has seen some solid evidence of it. “In copper technology, we have definitely seen a correlation between an increase in redundant vias and a decrease in field failures,” said Hirschi. “Redundant via failures are more a reliability mechanism than a yield mechanism, but we do have data we’ve correlated from that perspective. The company also has gathered some data suggesting that wire optimization and current analysis improves yield.

While users say it is hard to quantify DFM’s ROI, Cadence’s Deo said Cadence and IBM teamed up six months ago to perform an experiment in which they manufactured test chips with DFM and without DFM.

Deo said the companies did 14 wafer lots of manufacturing on a 65-nm process. In one design they used the traditional flow: place and route, rule based checking, and DRC. The next design they did place and route, then model as well as rule-based optimizations, and then taped out. Deo claimed there was a 7 to 12% yield improvement in the design that was done using DFM over the design that was not.

“I can’t talk about absolute yields but what we saw was that consistently every lot had better yield with DFM than without,” said Deo. “So when it comes to DFM you can only compare what you did before and what you are doing now. The biggest comparison comes from customers who have seen failures and we showed them where the failure was. It was after the fact for that particular design but now they have incorporate the technology in for their next-generation design and now they don’t see that kind of a failure. Quantifiably, we can’t say exactly what the ROI is but there definitely is ROI.”

Deo’s yield improvement claims certainly got the attention of panelist Ed Wan from TSMC, “That’s a big number, Nitin. … That’s a big number,” Wan said, responding to Deo.

Wan noted that DFM comes in many flavors: OPC and RET, Spice models model based proximity checks for OPC and litho simulation, and even design rules. “All those tools help improve yield,” said Wan. “DFM is like taking vitamins. … You can’t guarantee you will live longer but people do take them. It is something we encourage.” Wan said TSMC believes DFM helps TSMC’s customers bring more value to their designs, too.

Toppan’s Kalk said that unlike design, mask manufacturers can quantify the ROI of DFM and judges that ROI on three factors: improvements in mask quality, cost, or cycle time. “We can easily quantify the improvement in our cost or cycle time, but in yield we don’t really tend to see improvements,” said Kalk. “Manufacturing rules check has dramatically improved cycle times and reduced our inspection costs.”

In the audience, EDA industry analyst Gary Smith claimed that at a recent EDA event, TSMC’s vice chairman said that the foundry’s customers have not welcomed the idea of TSMC using RDRs (restrictive design rules) and thus TSMC has dropped their use of RDRs, at least for the time being. Smith wanted to know how TSMC was going to deal with that.

“We can demonstrate to the customer that there is a benefit to RDR, but I think one of the reasons there is resistance to RDR is because it does put a lot of restrictions on the way designers design their IP and their whole chip, and they are migrating a lot of designs from the past that are not RDR-compliant,” said Wan. “They see that as a big hurdle in terms of their design investment. I can see why there is resistance and hesitancy to using RDRs but at some point in time there may be no choice.” Wan later noted that foundries will be more successful in pitching RDR if “they draw a correlation that more RDR represents less variability.”

Wan and the other panelists all noted that at advanced nodes, process variability will become a much larger problem and that two perfectly DRC-clean designs will produce different yields strictly because of manufacturing variability. This will require greater use of statistical analysis tools and more comprehensive process models and will put tighter constraints on physical design tools.

“As we ratchet down the process variation becomes a larger impact,” said Deo. “Two completely clean designs will yield differently in manufacturing just because of variation in the process. That means the process variation will be highly dependant on the patterns on your chip. Who designs those patterns? Designers do.”

EDA vendors are making a concerted effort to integrate DFM tools into their traditional design flows and make the new DFM technologies transparent to users, so users won’t find the tools much harder to use.

But Hirschi said, as of today, if you are required to use DFM technologies to design in advanced nodes, it requires quite a bit of training, and designers are not so happy about having to add new tools and steps to the design process while they are still required to get designs out in tighter windows.

“I haven’t run across a designer yet at Freescale who has said I’m making his life easier,” said Hirschi.  “[DFM tools and techniques] do take additional time and additional training that we didn’t have to do in the past. As for the EDA vendors trying to make the tools as transparent as possible, I’m not sure that is very possible. We’ve formed a team at Freescale that works with design teams to cover the DFM portion of a design. We’ll do that until such time as they are able to do that on their own. I’m not sure when that will be,” said Ross.

Capodieci said that DFM power users are indeed in high demand and some designers have been smart repurposing themselves as such.

Five years ago, DFM start-ups began to pop up everywhere, but in the last few years, several of those have been acquired by larger EDA companies. Panelists noted that most of the good ones have already been acquired but said there is still room for improvement in DFM.

“There still are some small companies out there that we consider having solutions that are ahead of the game,” said Hirschi. “The big three will either come up with something to address that or absorb that company. We feel we have a good compliment of tools and there are few areas where we think we are weak and may plug them with point solutions but all in all we think we have a good suite.”

Capodieci said that tool interoperability would greatly help design groups with DFM. “What we prefer is neither point tool nor flows, we prefer interoperability -- well established interfaces, which are non-existent at this point,” said Capodieci. “Today the tools are there but the flows are not as smooth as they could be.”

Capodieci also called for EDA vendors to tackle data mining. “One thing DFM does is give you a much richer data set -- you can get architectural data, electrical data, design data, shape data, and process data all together. There is not any infrastructure capable of doing data mining. We are building all that ourselves and that is a missed opportunity for EDA vendors.”

Meanwhile, Hirshi said that as processes shrink, it’s going to become imperative that foundries provide accurate models of their processes as the processes evolve and work with EDA vendors to make sure those models are updated constantly and work with EDA tools.

Wan said that TSMC is on top of that issue already, sharing process data with its EDA partners via TSMC’s DDK (DFM design kit).