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Tela tackles growing lithography challenges without RDR

Instead of restrictive design rules, startup posits a pre-optimized, lithography-clean topology as a solution that even IC designers can love.

By Ron Wilson, Executive Editor -- EDN, 2/25/2008

The growing challenge of lithography is gradually backing the both the design and manufacturing communities into a corner. Starting as early as 90 nm, design teams had begun to suspect that rule-based lithography analysis was no longer up to the task—rulebooks were becoming rule encyclopedias, and even patterns that passed the rules could show unexpected variations in production. As geometries have continued to shrink, lithographers have struggled to maintain some sort of fidelity to patterns despite rapidly increasing Numerical Apertures and shrinking k₁s. Off-axis illumination, immersion optics, and resort to black magic have all been summoned to help.

Designers have tried to help as well, with OPC (optical proximity correction): a now-bewildering array of artifacts that are added to the basic patterns in the GDS-II file, either by rule or by model-based calculation, until the final mask images begin to resemble fractals. But still the problem has run ahead of the solutions.

This quandary has led some experts to suggest that in order to solve the problem, we will have to restrict it. The RDR (restrictive design rules) camp—a growing minority in the community—claims that the only resolution to the lithography challenge, short of EUV, will be to limit the kind and number of shapes we ask the lithography equipment to print in the first place. That relaxes the problem simply by limiting the number of pattern possibilities for which we must come up with OPC solutions.

The RDR idea has met with considerable opposition, both from designers who object to anything with the word "restrictive" in it, and from foundries who are unwilling to impose anything that could be objectionable to designers. But it has also received a big boost from one very influential source: Intel, which described its use of RDRs at 45 nm during last December's IEDM conference.

Now Tela Innovations, a startup company composed in part of cell-design experts formerly with Artisan Components (since acquired by ARM), has put another option on the table—not restrictive design rules, which would have to be traversed and enforced against a design database, but a fixed, pre-optimized, lithography-clean topology that forms the basis of all digital cells in a design.

The fundamental idea, according to Tela vice president of marketing Neal Carney, is to allow routing in only one direction per layer in the critical poly and M1 layers. "The shapes we produce are only rectangles—no bends," Carney says. This raises the immediate objection among cell designers and routing-algorithm people that design under such restrictions is next to impossible, and wildly inefficient. Not so, according to Tela.

On the question of possibility, Tela claims to have produced a commercially normal 800-cell library using a vocabulary of only about 60 unique patterns, all based on rectangles. Further, according to Carney, if you examine an entire functional block after all of the OPC rules are observed, use of Tela's patterns results in a 10 to 15% reduction in block area and a dramatic reduction in variations. The latter point is critical in that the most worrying litho-related variations at these layers translate directly into variations in threshold voltage, which in turn become variations in leakage current. So tighter control over litho variations can turn into lower static power.

Routing in only one direction means avoiding the bent shapes that cause the most severe problems for lithography. It also means it is relatively easy to insert dummy patterns to meet uniformity and pitch rules. All of these things lead to easier decoration and better results from both lithography and CMP (chemical mechanical polishing).

Nothing is free, of course. In order to achieve monodirectional routing in poly and M1, you effectively lose a routing layer. "That adds more vias to the design, and it can lead to a denser M2 layer," admits Tela CEO Scott Becker. And the placement process is a little different. "You are aligning through poly, not M1," Carney says.

But on the whole, the Tela concepts can drop into an existing methodology with only the addition of a few scripts in critical places, and the use of new libraries for cell-based portions of the design. Essentially nothing else needs to change. To hard IP or pad rings, the design just appears to be a typical gridded layout. The result on plots (see illustration, for instance) looks pretty much like any well-organized standard-cell design. But close inspection will reveal the one-dimensional nature of the routing.

At the moment, Tela is simply announcing its presence and describing its ideas. The company has been validating its notions by taking a 45-nm design through the flow at Qualcomm. Tela is awaiting a 45 nm test chip in March, using ring-oscillator patterns to estimate power and performance. Real functional blocks on silicon should follow on shuttles later in the year.

According to Carney, 45 nm is the point at which Tela's approach starts to show significant advantages, and by 32 nm it—or something very like it—may become the standard approach to overcoming the growing problems in lithography.

The company's model of engagement is service-and-IP-based. Tela would like to license its topology and provide the custom design work necessary to adapt a customer's existing libraries to the new approach. The company will start with digital libraries, but Tela is also investigating the implications for I/O circuits and, eventually, analog.

Finally, Becker has an interesting speculation about the future of the approach. He points out that today, a foundry must tune its front-end-of-line to accept any possible patterns that customers might throw at it. In reality, this means leaving a lot of potential density and variation control on the table. But if a foundry were to adopt the approach of pre-defined topology, it would be possible to tune the front end of the process to only the patterns actually used in the very limited set. At that point, the results could be rather dramatically different than what will be possible—at 32 nm say—using all the tools that we can throw at random patterns.