IBM, AMD demo first 'full field' EUV test chip

The industry leaders show the results of their work to integrate the capabilities of EUV lithography into a standard fab process flow.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 2/26/2008

At the SPIE Advanced Lithography conference being held this week in San Jose, research partners Advanced Micro Devices (AMD) and IBM announced a working test chip that uses extreme ultra-violet (EUV) lithography for the critical first layer of metal connections across the entire chip, compared to previous projects that utilized EUV for working chip components that were only “narrow field” and covered just a small portion of the design.

The work for the test chip was performed by AMD, IBM, and other partners at the UAlbany NanoCollege’s Albany NanoTech Complex, and the paper for it will be presented by Dr. Bruno La Fontaine of AMD at the SPIE conference today.

AMD noted that the paper will show successful integration of “full-field” EUV lithography into the fabrication process across an entire 22-mm by 33-mm AMD 45 nm node test chip.

“This important demonstration of EUV lithography’s potential to be used in semiconductor manufacturing in the coming years is encouraging to all of us in the industry that benefit from chip feature sizes shrinking over time. Although there is still a lot of work to be done before the industry can use EUV lithography in high volume production, AMD has shown it can be integrated successfully in a semiconductor fabrication flow to produce the first layer of metal interconnects across a full chip,” La Fontaine said in a statement.

“Collaborative research is essential to enabling advancements in semiconductor research," David Medeiros, manager of IBM’s patterning research in Albany, added in the statement. "Our partnerships at the Albany facility are allowing for assessment of the various aspects of the EUV infrastructure in an integrated way, and will be the true test of this technology’s readiness for manufacturing.”

The companies also reminded that as chip designers continue to add functions and increase the performance of their products, making the transistors smaller and smaller makes more transistors available within a given area, and how small transistors and the metal lines that connect them can be made is directly related to the wavelength of light that is used to project a chip design onto a wafer. Since EUV lithography uses a wavelength of 13.5 nm, significantly shorter than today’s 193-nm lithography techniques, traditional scaling of chip feature sizes can continue.

AMD’s test chip first went through processing at its Fab 36 in Dresden, Germany, using 193-nm immersion lithography, which is the most advanced lithography tool in high volume production today.  Then, the test chip wafers were shipped to IBM’s Research Facility at the College of Nanoscale Science and Engineering (CNSE)  in Albany, New York, where AMD, IBM, and their partners used an ASML EUV lithography scanner installed in Albany through a partnership with ASML, IBM, and CNSE, to pattern the first layer of metal interconnects between the transistors built in Germany. 

After patterning, etch and metal deposition and other processes, the EUV device structures underwent electrical testing at AMD, with transistors showing characteristics very consistent with those of test chips built using only 193-nm immersion lithography, and are set to receive additional metal interconnect layers using standard fab processing so that large memory arrays can also be tested.

AMD asserted that the next step in proving viability of the EUV lithography for production will be to apply it not only to metal interconnects but to all critical layers to show an entire working microprocessor can be made using EUV lithography. 

EUV lithography needs to be fully qualified for production prior to 2016, when the 22-nm half-pitch node on the International Technology Roadmap for Semiconductors is expected to be reached, the companies added.

Other work at CNSE includes EUV lithography experiements by IMEC, which is also working to speed the implementation of EUV lithography.