Synopsys expands IP portfolio with embedded memory

The semiconductor design software and IP giant is also collaborating with Novelics for SRAM-1T and low-power standard SRAMs.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 3/5/2008

To allow the design and manufacturing of higher performance and more power-efficient SoCs, semiconductor design and manufacturing software provider Synopsys Inc said today it is partnering with semiconductor embedded memory IP company Novelics to expand its DesignWare IP portfolio.

This technology licensing and development partnership covers the addition of SRAM-1T embedded memory IP into Synopsys’ DesignWare IP library, which is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs.

With content and feature-rich products requiring faster, more power-efficient SoCs with increasingly large amounts of on-chip memory, the company explained that high-density SRAM-1T memory IP allows integration of up to 3 times more memory than a standard 6T-SRAM, to allow chips to incorporate more system memory on-chip, and therefore lower power and overall system cost.

Synopsys noted that its DesignWare coolSRAM-1T is implemented on a bulk logic CMOS process and does not require additional masks or manufacturing steps in order to provide designers with a true zero-added-cost solution, promising up to 15% reduction in manufacturing costs compared to existing SRAM-1T products.

The DesignWare coolSRAM-1T memory IP is a compiler-based solution meant to give designers immediate access to specific memory IP instances without compromise on instance storage capacity or topology, the company added.

Further, Synopsys will also now offer a family of high-performance and low-power standard SRAMs that include single port 6T, dual port 8T, register file and ultra high density ROM.

The DesignWare coolSRAM memory IP is meant to allow the implementation of a 32Kb Cache memory operating well over 1GHz while drawing less than 6uW/MHz as measured on a leading 65-nm low-power process, with compilers including advanced power control features such as leakage control and block-level sleep mode to implement system-level power management, for increased battery life for portable devices.

Joachim Kunkel, VP and general manager of the solutions group at Synopsys added in a statement, “Embedded memory often represents well over 50% of the transistors on a chip, and therefore plays a crucial role in a designer's ability to differentiate their designs. Synopsys is expanding into this high growth IP market with a unique SRAM-1T embedded memory IP solution that allows designers to lower system cost and integration risk, while also offering a set of standard SRAMs that provides low power and high performance characteristics.”

The SRAM and SRAM 1T IP is set to be available this quarter.