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IMEC launches methodology to analyze process variability
Qualcomm and Samsung are currently partners in IMEC’s technology-aware design program, and IMEC has also signed a cooperation agreement with SI2 to pursue alignment with industry standardization effort for SSTA.
By Ann Steffora Mutschler, Senior Editor -- EDN, 3/14/2008
To allow for optimization of system designs for timing, energy and yield versus expected application load, Leuven, Belgium-based nanoelectronics and nanotechnology research center IMEC demonstrated this week a variability-aware modeling (VAM) flow that analyzes process variability of sub-45-nm technologies.
IMEC said the flow assesses the impact of process variations and degradation effects of sub-45-nm technologies on the system performance by giving valuable information to the designer and can hook into commercial design for manufacturing (DFM) tools.
The flow has been validated on industrial process technology data and IP cores, IMEC asserted.
Leveraging its expertise in advanced sub-45-nm process technology and system design technology, IMEC explained that it developed the VAM flow for percolating information on process variability of sub-45-nm technology from the transistor up to the system level.
VAM is meant to allow IP block and system designers to make predictive assessment of architecture design options and to identify design bottlenecks before manufacturing in order to overcome functional problems and parametric uncertainty of designs caused by process and material variability of deep sub-micron technologies.
Further, IMEC said it validated the VAM flow by propagating commercial TSMC 45-nm variability data to estimate performance and energy for an ARM926 processor. The VAM output was used to optimize the processor before manufacturing using a commercial toolflow.
Rudy Lauwereins, VP of nomadic embedded systems at IMEC noted in a statement, “Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fablite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies. To this end, we invite IDMs, fabless system companies, fabless digital IP providers and foundries to collaborate within our technology-aware design program to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC’s program is compatible with confidentiality constraints for high value proprietary IP blocks.”
Qualcomm and Samsung are currently partners in IMEC’s technology-aware design program, and IMEC also signed a cooperation agreement with SI2 to pursue alignment with industry standardization effort for SSTA.
