Intel fleshes out next-gen multicore processors

The chip giant detailed its Tukwila, Dunnington, Nehalem, and Larrabee processors.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 3/17/2008

As part of a preview to the April Intel Developer Forum being held in Shanghai, China, Patrick P. Gelsinger, Intel Corp’s senior VP and general manager for the digital enterprise group, today once again provided evidence that the chip giant continues to maintain its leadership position ahead of challenger Advanced Micro Devices.

Starting out a press call by reminding that its “Tukwila” quad-core processor is on the way, Gelsinger confirmed the chip contains 30 MB cache, 2 billion transistors, multi-threading technology, and the company’s QuickPath interconnect. Also, Tukwila boasts dual integrated memory controllers, an estimated 2X performance gain compared to Intel’s dual-core Itanium 9100 series processors and mainframe-class RAS – all aimed at high-performance servers.

He then discussed the “expandable and scalable” quad-core Xeon processor 7300 series, also known as “Caneland,” which was specifically built for virtualization and consolidation in data centers, bolstered by energy-efficient performance that he claimed leads in benchmarks, for enterprise-proven reliability and investment protection.

Gelsinger then introduced “Dunnington,” which he said during IDF, “will show the most extensive virtualization ever done.” Dunnington is a 6-core processor with 1.9 billion transistors, manufactured on Intel’s 45-nm high-k technology, with 16 MB of level 3 cache, socket compatible with Caneland, and is set for availability in the second half of this year.

The Nehalem micro-architecture, next on Gelsinger’s agenda, is set for production in Q4, and is a dynamically scalable processor, which he explained means can be scaled from 2 to 8 cores within its 4-wide micro-architecture enhancements. The architecture allows for 2-way simultaneous multi-threading, contains an integrated memory controller, QuickPath Interconnect, shared and inclusive level 3 cache, dynamic power management and SSE 4.2, he confirmed.

One of the keys to Nehalem, Gelsinger noted, is its scalable design via modularity that allows developers to access the Nehalem building block library to customize product options by varying the number of cores or blocks within the design.

Further, Intel made core enhancements to the Nehalem microarchitecture for increased parallelism, support for enhanced algorithms and further branch prediction enhancements, all of which build on Intel’s Core micro-architecture. Another key addition is support for simultaneous multi-threading (SMT), which allows each Nehalem core to execute two software threads simultaneously and is a critical technology for multicore processing, particularly for highly-threaded workloads such as multi-media applications, databases and search engines, along with multi-tasking scenarios.

For multi-level shared cache, Nehalem also now contains a new 3-level cache hierarchy including new 256KB/core, low latency L2 cache, and a new large 8MB fully-shared L3 cache, along with a new 2-level translation look-aside buffer.

For high end desktops and server/workstations, Gelsinger detailed the Nehalem/Tylersburg platforms with aim for huge latency decreases and bandwidth increases over the prior generation with QuickPath interconnect and an integrated DDR3 memory controller.

With plans for first demonstrations later in the year, Intel said its Larrabee architecture is the next step in evolving the visual computing platform, as it includes a high-performance, wide SIMD vector processing unit (VPU) along with a new set of vector instructions including integer and floating point arithmetic, vector memory operations and conditional instructions.

Larrabee also contains a new hardware coherent cache design meant to allow the many-core architecture, whereby the architecture and instructions have been designed to deliver performance, energy efficiency and general purpose programmability to meet the demands of visual computing and other workloads that are inherently parallel in nature.

And as tools are critical to success, Intel said key software products will be enhanced to support the Larrabee architecture to allow developer freedom. Industry APIs such as DirectX and OpenGL will be supported on Larrabee-based products.

Finally, Gelsinger discussed Intel’s advanced vector extensions (AVX) which, when used by software programmers, are meant to increase performance in floating point, media, and processor intensive software as well as increase energy efficiency, and is backwards compatible to existing Intel processors.

Key features of AVX include wider vectors, increasing from 128 to 256 bit wide, resulting in up to 2x peak FLOPs output, with enhanced data rearrangement resulting in data being allowed to be pulled more efficiently, and 3 operand, non-destructive syntax for a range of benefits.

Intel plans to make the specification public in early April at the Intel Developer Forum in Shanghai, with instructions to be implemented in the microarchitecture codenamed "Sandy Bridge" in the 2010 timeframe.