Spansion boosts efficiency at 2 fabs

The dedicated flash memory maker attributes new testing capabilities to increases in both throughput and yield, specifically for products manufactured at the 65-nm process node including the company's MirrorBit flash memory.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 3/19/2008

Sunnyvale, Calif.-based dedicated flash memory company Spansion Inc reported today that it expects to reduce its reliance on foundry and subcontractors by approximately $50 million per quarter in the first half of fiscal 2008 compared to the second half of fiscal 2007, thanks to manufacturing efficiencies.

Efficiency measures are resulting in increased output in Spansion’s Austin, Texas Fab25 and Aizu-Wakamatsu, Japan-based SP1 fab and are expected to allow the company to reduce its dependency on outside foundry support, particularly for products at the 90-nm manufacturing node.

Spansion also attributes new testing capabilities to increases in both throughput and yield, specifically for products manufactured at the 65-nm process node including the company's MirrorBit flash memory.

Bertrand Cambou, president and CEO of Spansion said in a statement, “Last year, Spansion committed to reducing dependencies on external foundry sources and streamlining our own manufacturing and test capabilities, with the ultimate goal being significant cost savings. With the exceptional performance of our worldwide manufacturing and engineering teams, we have met that challenge and are committed to continuing to prove our ability to lead in this highly competitive field.”

In addition to its internal manufacturing focus, the company said it also plans to continue its long-term partnership strategy with a select group of subcontractors, including ChipMOS for wafer sort and SMIC for wafer foundry services, with the SMIC agreement expected to result in 65-nm, 300-mm wafers being produced before the end of fiscal 2008.

Specifically at Spansion's Fab25 in Austin, the company said results continues to exceed expectations in both yield and output on 90-nm products, while at SP1 in Japan, the fab has ramped up on 300-mm wafers, reaching starts of 2,000 wafers per week on 65-nm MirrorBit technology flash memory products.

The company also reminded that plans for SP1 include an aggressive migration plan to 45-nm in fiscal 2009, which is expected to provide additional cost efficiencies.

In terms of test, Spansion said it has been developing new capabilities for wafer-level testing and built-in self test (BIST), designed for integration with 65nm lines, which is expected to result in higher throughput, increased yields and lowered costs. 

By integrating these testing capabilities into its existing facilities, Spansion said it has reduced its dependencies on external test vendors, which has resulted in cost reductions, with wafer-level testing streamlining the overall testing process by conducting electrical testing while the die are still in wafer form, reducing the amount of time spent on identifying design or processing problems. 

Specifically designed to reduce costs associated with testing, the company noted that BIST is meant to reduce both the test cycle duration and the complexity of the test set-up, which directly reduces the need for automated test equipment.  These advanced techniques for testing provide faster, more accurate measurement results, providing an increased return on investment, Spansion concluded.