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Statistical timing gets a foothold in leading-edge designs
Events at ISQED spur discussion as to whether, and at what node, statistical techniques are necessary.
By Ron Wilson, Executive Editor -- EDN, 3/24/2008
Is statistical timing analysis really helping anyone, or is it an EDA-industry marketing ploy? This simmering debate within the leading edge of the chip design community bubbled to the surface in the plenary sessions Wednesday during the International Symposium on Quality Electronic Design (ISQED). The topic was the subject of both a lunch-time panel discussion and a plenary paper by one of the founders of the sport, IBM's Chandu Visweswariah.
There was little argument in the panel discussion as to whether statistical timing actually did anything: No one challenged the underlying theory. There was discussion as to whether, and at what node, statistical techniques were necessary. On one hand, predictably, Visweswariah backed the approach, pointing out that IBM now required full-chip statistical timing analysis on all designs at 65 nm, both for timing closure and for sign-off.
On the other side of the discussion, Sequence Design's Rob Matthews argued that at least at 65 nm, extracting what he called "statistically accurate corners" could achieve much the same result as statistical timing analysis. He described the technique only briefly, saying that designers extracted corners in the normal way, then applied statistical tools to relax the margins at these corners from the worst-case levels to something approaching 3-sigma levels of variation. Matthews said that NEC had been applying this technique at 65 nm on selected, timing-critical blocks, and had achieved 20 to 30% reductions in excess margins.
Cadence's Vinod Kariat added weight on the skeptical side, pointing out that at 65 nm "there is still a lot of spread in techniques. Many 65 nm designs are done without statistical timing," he maintained.
Part of the reason for this, Kariat speculated, is that there are many reasons for moving to the 65-nm node, only one of which is performance. If the power-performance product isn't a critical issue on the design, the relaxation of timing margins you can achieve with statistical techniques may simply not be worth it. And there are other alternatives even if timing is critical, Kariat pointed out. You can employ conservatively designed cell libraries and restrictive interconnect rules at critical metal levels to in effect design-out variations. You can model systematic variations accurately and account for them in timing models. Or you can simply margin the design a little more, as we have always done in the past. "Design teams can use any or all of these techniques in combination," Kariat said. "How you use them depends on what you are trying to accomplish in a block."
Kishore Singhal of Synopsys agreed that the use of statistical tools was a question not of if, but of where. He pointed out that Monte Carlo analyses of small circuits had been used in the precision-analog and RF design worlds for decades, and later they were applied in cell design, as well. But Singhal emphasized that there were some issues. For one, fab statistics—the data upon which statistical analysis rests—are not, in the technical sense, stationary. In order for the technique to be safe, foundries would have to augment their internal control systems to stabilize long-term shifts in process variations.
Finally, Singhal pointed out that the whole point of statistical timing analysis was not to reduce excess margins, it was to increase profits. "This is something some experienced design managers understand, but I don't think it's something we can teach widely," Singhal said. "We need a tool that will analyze a design and produce a single metric: dollars."
Other speakers came back to the question of simplicity and adoption. "Teams aren't measured on their use of statistical techniques, they are measured on getting designs out," observed Kariat. "If statistical timing makes closure quicker, it will get used."
Visweswariah said that statistical timing only began to make sense as you approached tape-out. "Early in the design, when there are large uncertainties anyway, single-corner analysis is fast and just fine."
Kariat agreed that adoption of statistical tools would be phased. "I think a lot of people will do sign-off with corner-based analysis. But they will use statistical tools to look at specific difficult problems, until they build confidence with the technique."
In a separate paper earlier in the day, IBM's Visweswariah brought up another dimension in the statistical analysis debate. He pointed out, bluntly, that the Wafer Acceptance Criteria foundries use during metrology to decide whether to stop processing a wafer are not directly coupled to the electrical variation margins established by design teams. "You have to live with the idea that on 'good' wafers, two or three parameters will be outside your 3-sigma limits," he warned. This means that high-yielding designs are robust with respect to process variations. And robust, in this case, simply means that the timing and power have low sensitivities to the known sources of process variation.
With this reality in mind, Visweswariah said, IBM had developed a report from its statistical tool that showed slack versus sensitivity for each source of variation tracked by the tool. This could amount to a dozen, or dozens, of individual variations from different processes steps, and of course an entire chip full of paths. With this report, timing closure required not only ensuring that timing slack was positive, but ensuring that if positive slack were small, the sensitivity of that net to process variations was also small.
What does this mean in practice? Visweswariah said that making a design more robust may require a systematic fix. Or it may be sufficient to make specific repairs, such as moving a few long traces off of metal-3, if metal-3 is showing a particularly high sensitivity to metal-thickness variations. The emphasis is not on statistical timing analysis as a pushbutton tool—although IBM does use if for sign-off—but on the tool's ability to give designers visibility into the risks they are taking, so they can make informed decisions.
