Georgia Tech studies off-chip-interconnect issues

As chips get faster, off-chip interconnect increasingly looks like a bottleneck to high-frequency signals. This scenario occurs when the signals must traverse not only relatively long distances across a board, but also short hops from the package leads to the board traces. A pair of studies at the Georgia Institute of Technology School of Chemical and Biomolecular Engineering is exploring these challenges.

In the first study, researchers attempted to fabricate an all-copper structure to bond package-lead frames to PCBs (printed-circuit boards), reasoning that such connections should be lower in series resistance than the traditional flow-soldered-bump technology. The team electroplated copper bumps onto both the package pads and the PCB pads. Then, placing the package on the board and aligning the bumps, they immersed the assembly in an aqueous-copper solution, allowing a thin pillar of metallic copper to grow between the bumps.

The result is too thin to be structurally adequate in that state, so the team then annealed the assembly at 180°C for one hour—not necessarily the most welcome step for process engineers but enough to strengthen the copper pillars. The result is a strong, low-resistance connection.

For board-crossing, the second study experimented with forming conductors with buried air gaps beneath them to reduce parasitic capacitance. The process involves plating copper traces onto an epoxy-fiberglass board and then coating the traces with a layer of sacrificial polymer. A layer of a different polymer then builds up around the traces. A titanium barrier and a top copper layer go over the original traces on top of the sacrificial polymer. The scientists then cook away this sacrificial polymer at 180°C. The result is a multilayer connection of copper, air gap, titanium, and copper.

The team has demonstrated formation of this structure and is working on a version that would in effect form a coaxial cable.