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Working group plans low-power serial DRAM interface
Proposed SPMT (Serial Port Memory Technology) would start by drastically simplifying handset design.
By Ron Wilson, Executive Editor -- EDN, 4/29/2008
The rise of the cellular handset has revolutionized thinking on integrated systems architecture in many ways, from multiprocessing SOCs (systems on chip) to RF circuitry on CMOS logic chips. But the one area of the handset that has arguably been most resistant to change has been the DRAM. Handset designers still labor with a version of the DDR interface originally designed for the personal computer. If a new DRAM working group announced this morning has its way, that is about to change.
The group is proposing that DRAM designers integrate a high-speed, multilane serial interface into their parts in place of the existing parallel DDR synchronous interface. This, the group says, would slash power consumed in I/O, simplify board design, and reduce latency in memory transactions.
The SPMT (Serial Port Memory Technology) group currently comprises ARM, Ericsson, Hynix Semiconductor, LG Semiconductor, Silicon Image—which appears to be driving the effort—Samsung, Sony-Ericsson, and STMicroelectronics. Other companies, including at least one more major DRAM player, are said to be participating but have not yet announced.
The SPMT plan, according to Jim Venable, Silicon Image's director of advanced memory technology, is to develop a specification for a multilane serial interface conceptually like PCI Express, but optimized for DRAM interfaces and therefore very different in details. The interface would employ differential-pair signaling transmitting 5 Gbps per pair. DRAM chips would use multiple pairs per port to achieve transfer rates from 800 Mbytes/sec to, eventually, 12.6 Gbytes/sec. The approach would require no changes to the DRAM core design, bank and buffer organization, or process technology.
Architecturally, the concept takes into account the existence of multiple processing sites in a modern handset. A DRAM would have multiple ports, with, for instance, one port dedicated to the baseband processor, another to the applications processor, and a third to a video/graphics engine. Rather than include a port arbiter on the DRAM, which the study group judged prohibitively expensive, the scheme depends on policy-based arbitration among the processors.
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Venable says that the working group is not yet ready to release technical details of the proposal. But some points are available. Electrical signaling is low-voltage and differential, but optimized for the very short point-to-point interconnect runs characteristic of handset motherboards and stacked-die systems-in-package. Thus the proposal differs considerably from LVDS.
Similarly, the SERDES is greatly streamlined, according to Silicon Image. The designers have focused on very fast framing and low energy consumption, for example eschewing the 8b/10b encoding typical in other serial links. Thus the links are able to achieve low latencies and relatively short message lengths over the distances required.
The projected results are impressive (see table). An SPMT DRAM designed for 800 Mbyte/sec maximum transfer rate would require only 10 pins, versus the 53 pins required for the same data rate in LPDDR2. The link would require 40 mW for I/O at this rate, compared with LPDDR2's 60 mW. Things look better at higher aggregate data rates, Venable says. To achieve 3.3 Gbytes/sec, the SPMT DRAM would need only 20 pins, compared with 69 for the LPDDR2 device, and would dissipate 120 mW, instead of 220 mW, in I/O power.
The working group is not soliciting new members, but intends to form Contributor and Adopter Groups once the specification is ready. The group has said nothing publicly about working with or through JEDEC (Joint Electron Devices Engineering Council). But that doesn't mean the proposal will be confined to the handset community. Venable says he expects "SPDRAMs," as he calls the anticipated memory chips, to spread from the smartphone application area down-market into less complex handsets, and then out of handsets into the many other areas where low pin-count, simplified routing, and low I/O power would be valuable.
