Voltage-aware simulation: No longer a fad, but a must for low-power designers

GUEST OPINION: With multiple power domains, traditional on/off simulation loses accuracy and misses bugs.

By Krishna Balachandran, Synopsys -- EDN, 5/14/2008

Advances in process technology have enabled more transistors than ever to be packed in a die. The transistors have become smaller than ever. The net result is that the power density or power dissipated per unit area has gone up tremendously. Design-for-power is the new catchphrase. Fundamentally, these design techniques are about turning off unused parts of the design, and increasingly sophisticated techniques are being employed to do so. Until recently, verification techniques have not kept pace with design, leaving low-power designs exposed and prone to power-management bugs.

Traditional verification techniques have focused on 0-1 logic functional simulation. That approach was sufficient when designs were driven by a single voltage that could be turned on or off. Contemporary design techniques involve using multiple voltages to drive different parts of the design. Each of the different power domains may even operate at multiple voltage values. Verification must comprehend not only the on/off behavior of the power domains but also the effect of varying voltages over time and the interdependencies with respect to each other.

With multiple power domains, traditional on/off simulation loses accuracy and misses bugs. Consider the case when a power management unit generates multiple voltages for different power domains. A buffer in a power domain driven by 1.2V drives logic in another power domain operating at 1.5V. Traditional on/off simulation will treat both values as logic 1 and propagate logic 1 downstream. Most technologies typically consider 70% as the threshold for logic 1. Using the 70% test, a voltage-aware simulator will resolve the voltage from a 1.2V power domain as a logic 1 for the 1.5V power domain. However, if the power-management unit generating the voltage for the 1.2V power domain fluctuates and the voltage drops to 1.0V, the reduced voltage will fail to meet the criterion to be evaluated as a logic 1 for the 1.5V power domain. The correct simulation behavior should be to identify the 1.0V as too weak to be considered logic 1 and show corruption of all downstream logic in the 1.5V power domain. Traditional on/off simulation will not do this. A voltage-aware simulator will correctly resolve the voltages and faithfully identify the design bug of a missing level shifter between the two power domains.

So, what would happen if a designer were to rely on older verification tools? The design would pass functional verification and behave erratically whenever the signal traveled from the 1.0V domain to the 1.5V power domain. Worse, the problem would be found only in silicon, and it would take an expensive team of reliability engineers to debug and fix the problem, not to mention a re-spin—with all the associated mask costs and lost time-in-market.

A voltage-aware verification solution can save the day by responding to the challenges posed on verification by the complex techniques used by designers of low power or power-aware chips. At each point in the simulation, it keeps track of all relevant voltage values, and resolves the outputs based on the interaction of the voltage values. It therefore is truly able to mimic silicon behavior and mitigates the risk for missed power-management bugs.

With the increasing adoption of low-power design techniques, it behooves the designer to adopt a bulletproof verification solution. As President Reagan said, "Trust but verify." No low-power designer can afford to neglect such good advice, not anymore, not when a re-spin can cost more than $1 million in a 65-nm process. Voltage-aware simulation is no longer a new fad, it is a must for the savvy designer.

Krishna Balachandran is director, low power verification marketing, with Synopsys.