Applied, IIT-Bombay, SRC team to advance NAND technology

The Indian university and semiconductor manufacturing equipment leader presented research at a recent physics symposium that showed as NAND flash devices continue to scale, problems with reliability and lifetime caused by cell-to-cell interference arise when conventional floating-gate (FG) memory cells are used, and that charge-trap flash (CTF) is a promising replacement for FG because it exhibits negligible cell-cell interference, yet has a similar structure and manufacturing process to FG.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 5/20/2008

In an effort to advance the rapidly evolving NAND flash memory technology and develop breakthrough technology leading to significantly smaller and more powerful portable electronic devices in the next five years, the Semiconductor Research Corp (SRC), working through its global research collaboration program, said it will collaborate with the Indian Institute of Technology at Bombay (IIT) www.iitb.ac.in and semiconductor manufacturing equipment leader Applied Materials Inc.

IIT and Applied presented research at the recent International Reliability Physics Symposium in Phoenix, Ariz. that showed as NAND flash devices continue to scale, problems with reliability and lifetime caused by cell-to-cell interference arise when conventional floating-gate (FG) memory cells are used, and that charge-trap flash (CTF) is a promising replacement for FG because it exhibits negligible cell-cell interference, yet has a similar structure and manufacturing process to FG and is thus attractive for memory device manufacturers to implement using existing equipment.

David Kyser, senior director of strategic external research in Applied’s department of advanced technology/CTO commented in a statement, “IIT is deeply engaged in NAND flash memory research and has been an excellent partner in helping us to continue to drive solid-state memory technology development. This type of collaboration, facilitated by SRC, is an efficient way to drive the commercialization of new technologies: Industry provides near-term focus while academia brings innovation and scientific rigor.”

The companies are working primarily on development and optimization of an engineered trap layer consisting of two nitride layers with different compositions, reinforced by a silicon oxy-nitride barrier layer, which was found to exhibit negligible cycling degradation and optimum programming characteristics, offering an alternative to approaches using more complex high-k and metal gate materials.

This new structure has the potential to scale down to the sub-3xnm technology node, offering much higher storage densities than are available today, the companies believe.

“Materials development and process integration are the keys to implementation of the new cell designs. The diverse, but complementary, perspectives among this team of researchers have served to more quickly uncover the physical mechanisms of endurance damage. These have provided for better understanding of reliability and consequently improved device design,” noted Souvik Mahapatra, associate professor in the department of electrical engineering at IIT-Bombay.

The SRC said the collaboration reflects SRC’s commitment to tapping the deep talent offered by Indian research and the potential for significant progress in memory design, with the success from this work expected to lead to higher standards for functionality in future electronics.