Achieving first-time success at 40 nm

Every process generation brings new design challenges, but, for the 40-nm node, both the difficulty and the risks are exceptional. Increased complexity, size, and design costs dictate that designers adopt new methodologies to ensure that they get it right the first time (Figure 1). Systematic use of test chips and enhanced statistical simulation are some keys to successfully addressing 40-nm-process-generation challenges.

Designers moving to adopt a 40-nm-process technology face substantial risks. The new process comes with new design challenges to address, and the penalty for error is high. Mask costs grow about 50% each generation, and, for the 40-nm process, they currently exceed $3 million. Equally important, the cost of the design effort is growing—more rapidly than mask cost—because of increasing gate count and chip complexity. Designers, therefore, need to adopt methods that will allow them to address both the financial and the technical challenges of process migration (see sidebar “Bimodal-process-technology adoption”).

One of the most important moves that design teams can make is to adopt a methodology of verifying blocks in silicon using test chips early and often during the design. Altera adopted this approach for the 90-nm generation and has carried it over to the 65- and 40-nm generations to achieve high success with first production silicon. The approach supports design reuse to save development cost and helps the design team understand and resolve new process-design challenges (see sidebar “Analog challenges versus process-node shrinkage”).

Test chips help address numerous design issues by validating both the circuit design and the process characteristics (Table 1). The first test chips, which designers run early in their efforts, can contain simple logic blocks and interconnects or single transistors. The design of these test chips can begin before the process and simulation models are stable, giving developers a head start on process migration. These tests help validate some design rules and indicate where other rules need modification, ensuring that the circuitry will perform as expected in the final design. Testing at this stage, however, requires design teams to work closely with their foundry to understand the deep-submicron issues that arise.

Test chips also help to account for new deep-submicron effects that arise with a change in technology node. Sometimes, these new effects become more apparent in actual circuits than they were in simple process-test structures. Then, a test chip behaves unexpectedly. By undertaking a correlation exercise, the design team can help identify effects they had not previously understood. Test chips can also identify circuit sensitivity to effects that the designers knew about but did not fully appreciate.

Later in the design process, when all important effects are known and when the design rules are more stable, test chips allow designers to evaluate larger blocks. At this stage, teams can also try to reduce design layouts or new layouts of logic designs to determine whether they function adequately in the new process. The results of such tests help teams define their strategy for both hard- and soft-design reuse to save development time and cost. If functional problems appear or the block’s performance needs improvement, designers have an opportunity to make the necessary changes early in the project. Blocks that traditionally need fine-tuning include memories, PLLs (phase-locked loops), and high-speed I/Os. They are prime candidates for testing at this stage.

As the design progresses, test chips allow designers to evaluate the integration of blocks into larger structures. The chips also provide an opportunity to evaluate any modifications the team made as a result of earlier testing. Depending on how many test chips they run during the development effort, designers may have several opportunities to repair or enhance their blocks before the design becomes final. Altera’s development efforts may involve as many as nine test chips during a product design, typically every three to four months.

This use of test chips greatly increases the chances for first-time success when you fabricate the full design, but the approach might appear costly at first because it involves so many mask sets. Collaboration with the foundry as well as the use of shared-cost programs, such as the TSMC (Taiwan Semiconductor Manufacturing Co) Shuttle program, however, can keep down the cost of test chips. During process development, for instance, the foundry must run numerous test wafers to fully characterize and tune its fabrication methods. It also periodically runs test wafers to monitor the process. A close working relationship with the foundry provides opportunities to piggyback simple test structures on the foundry’s own wafers in the early stages of a design. The Shuttle and similar programs allow testing of larger structures or even full designs. A 3×4-mm die in a 40-nm shuttle costs less than 5% of a full mask set, allowing several iterations of the final design for less than the price of one production-mask-set revision. The total mask cost of the test-chip program may exceed the cost of one mask-set revision, but the design-effort efficiencies you gain in areas such as design reuse and early error detection can largely offset the test costs.

Along with adopting new design methodologies such as the test-chip program, developers embracing 40-nm technology need to enhance their methods and design parameters. Three areas that are particularly important in this process generation are process variability, power management, and high-performance analog. Although these problems are well-known in earlier process generations, 40-nm technology puts a unique spin on them.

Chip developers have long been aware of and have accommodated process variability at the chip level. Monte Carlo statistical simulations guide designers in creating chips that will work properly when their transistors vary as much as three standard deviations (three sigma) from the production mean. But these techniques address only wafer-to-wafer variations and chip-to-chip variations within a wafer. In a 40-nm process, features are so small that the placement of individual atoms can have a measurable impact. Gate oxides, for instance, are now only a few atoms thick. You can no longer consider the dopant in transistor channels relatively uniform. Instead, the placement more closely resembles a dash of salt grains scattered across a plate, on which each outlined square is one random distribution with an expected value of 50 dopant atoms (Figure 2). The actual number of atoms—37, 45, and 60, respectively—for these three trials shows that, in addition to having a random spatial distribution, the total number of atoms within each square varies.

This dependency on individual atomic placement introduces an unprecedented degree of local variability to circuit behaviors. Robust statistical-analysis and modeling tools, which accurately account for local variation, enable designers to optimize their circuits in the presence of local variability. The ability to accurately model local variation is especially critical for the design of high-yielding memory and analog circuits. For parameters such as standby current, only the total current across a die is valuable. In this case, local variations above or below the average tend to cancel each other out.

In addition to designing for greater variability, developers should begin to incorporate redundancy to improve chip yields. This step is particularly important for the large dice of today’s complex designs. With a large die, even a small change in the defect density in production can have a major impact on yield. On-chip redundancy allows the design to bypass defects instead of simply failing. You need to weave this redundancy into the architecture at the circuit level, however, not add it as an afterthought.

Developers should also consider lowering the circuit power. As process technology shrinks, circuits become faster and denser, and chip power rises in proportion. For many applications, however, chip power is more important than performance. Many applications require more functions in next-generation chips without increasing power requirements, and higher performance holds only secondary importance.

The traditional approach to lowering power has been to lower the supply voltage to offset the greater number of transistors. But transistor-threshold levels do not scale with process technology, so lowering the supply voltage reduces the margin within which the transistor operates. Local variations further reduce that margin. The lower the supply voltage, the greater the significance of predicting and accounting for local variability—specifically, for threshold-voltage variations.

In addition to lowering supply voltage, designers must adopt other approaches to reducing chip power. Altera has traded performance for power at both the transistor and the architectural levels. Increasing the threshold voltage of a transistor, for instance, slows it but reduces its leakage current. Similarly, increasing channel length slows a transistor but lowers its switching current. You can make numerous other such trade-offs at the transistor level.

At the architectural level, designers can trade performance for power on each circuit. In an ASIC design, this kind of trade-off is static. Analyzing the performance needs of a circuit identifies the critical paths on which high speed is necessary, allowing designers to assign faster transistors on those paths and use slower but less power-hungry transistors elsewhere. In an FPGA for which you don’t know the critical path before programming and in other applications in which circuit speed may vary, a more dynamic trade-off is necessary. Reverse-back-biasing a transistor increases the threshold voltage, thereby reducing the power. Design tools can automatically adjust the back bias of the transistors based on a specific program to optimize speed and power.

Finally, designers must address the challenges of mixed-signal design. Many devices now need to incorporate high-speed transceivers. Even for purely digital logic, analog and high-frequency circuit content is increasing to support such functions as high-speed serial I/O. Successful implementation of such functions requires circuit components optimized for high-speed-analog-circuit design, but their requirements are often at odds with the requirements for high-speed-digital-circuit components. This discrepancy is becoming more pronounced as process technology scales down.

The key to solving this dilemma is working closely with the foundry early in process development to ensure adequate optimization of the essential components for high-speed-analog design. Developers can also populate a significant portion of their test chips with analog components to help develop accurate simulation models. Placing one whole channel of a high-speed transceiver on a test chip, for instance, gives an opportunity to evaluate the parasitic effects of interconnects; model on-chip resistors, capacitors, and inductors; and see how well the design will work. This use of test chips allows designers to predefine analog components and fully characterize them to minimize mismatches in the final design.

Collectively, all these efforts addressing analog design, power trade-offs, local variability, and the use of test chips work together to ensure first-time success in 40-nm design. Further, the methods that address these problems will be applicable when it comes time to make the next process migration. New technical challenges will arise, but the methodology provides the opportunities to resolve those challenges, keep costs down, and achieve success with first production silicon.

Author Information

Mojy Chian is vice president of technology development at Altera Corp. His responsibilities include process-technology definition, implementation, and design infrastructure for new technologies, as well as yield improvement, defect-density reduction, and factory control for mature technologies. He holds bachelor’s, master’s, and doctorate degrees in electrical engineering as well as a master’s degree in applied math from the Florida Institute of Technology (Melbourne, FL).

Richard Cliff is vice president of IC design at Altera Corp. He has led the hardware development for the Stratix, Apex, and Flex device families and holds more than 100 patents in programmable logic. He has a bachelor’s degree from Manchester University (Manchester, UK).

Jeff Watt is a technology architect at Altera Corp, where he oversees compact-model development. He has master’s and doctorate degrees in electrical engineering from Stanford University (Palo Alto, CA) and a bachelor’s degree in electrical engineering from Queen’s University (Kingston, ON, Canada).