Low-power environment targets chip design

Further backing its support for the UPF (Unified Power Format) for ex-change of power-related design data between EDA-chip-design tools, Synopsys has assembled a comprehensive array of tools for achieving power-related design objectives. The Eclypse tools span system-level, verification, implementation, sign-off, and IP (intellectual-property) methodologies and services for low-power-chip development.

Synopsys will host a series of low-power-design seminars as part of its promotion of the concept. Using the tools, the company says, you will be able to apply techniques such as multithreshold-CMOS-power gating and multivoltage and dynamic-voltage and frequency scaling in a less time-consuming manner, requiring less manual verification.

The company based the suite on the Low-Power Design Methodology Manual, which Synopsys and ARM  co-authored; the approach also extends to the Innovator environment for embedded-software design. In that context, you can run software on a virtual platform using fast models of processors and IP blocks.