IBM, Toppan expand photomask development to include 22-nm node

The development agreement covers the last phase of 32-nm photomask process development, and all phases of 22-nm photomask process development, the work for both of which will take place at IBM’s Burlington photomask facility in Essex Junction, VT., starting this month.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 6/19/2008

Building on joint progress at the 45-nm and 32-nm semiconductor manufacturing nodes, and with an aim to drive the advanced photomask technology needed for next-generation chip manufacturing production, IBM  and Tokyo-based photomask company Toppan Printing Co Ltd have entered into a new development agreement covering photomask process development including early establishment of a 22-nm photomask process.

Last week Toppan announced what it believes is the industry’s first 32-nm photomask manufacturing process, set to begin volume production this month.

The development agreement covers the last phase of 32-nm photomask process development, and all phases of 22-nm photomask process development, the work for both of which will take place at IBM’s Burlington photomask facility in Essex Junction, VT., starting this month.

The companies reminded that photomasks are used to transfer semiconductor chip circuits onto a silicon wafer, and is a critical first step in semiconductor production.

As semiconductors have become increasingly sophisticated due to growing demand for telecommunications devices and highly complex and multifunctional digital consumer electronic products, it is therefore vital that semiconductor and photomask manufacturers work closely together to develop the advanced lithography technologies that will be needed to produce future-generation semiconductor chips. 

In order to stay on track with keep pace this technology, Toppan and IBM began jointly developing 45-nm photomasks in 2005, and expanded the scope of their activities to include 32-nm development in 2007.

Further, Toppan said it has already developed a 32-nm photomask process at its facility in Asaka, Japan, and as part of its activities with IBM, will work to integrate the Toppan process into the 32-nm photomask process that the companies will develop together, with the aim of optimizing the performance. (A prototype of a photomask incorporating Toppan’s system design is pictured left.)

Options for 22-nm

In terms of semiconductor manufacturing at the 22-nm node, the industry is considering implementation of many new technologies such as extreme ultraviolet (EUV) lithography and nano-imprint, but many technical issues have yet to be solved, the companies noted.

The joint IBM-Toppan 22-nm photomask process will include argon fluorine (ArF) immersion lithography, which is the current mainstream technology for the manufacture of 32-nm photomasks.

“This newest process development agreement with Toppan Printing builds upon the success that our two companies have enjoyed while working together over the past several years. This newest agreement will help ensure we can continue to deliver innovative chip applications for IBM systems and our OEM semiconductor clients. This collaborative effort builds upon our joint progress at 45-nm and 32-nm and sets us on a path to deliver the photomasks needed for next-generation chip manufacturing production,” said Michael Cadigan, general manager of IBM semiconductor solutions, in a statement.

Naoki Adachi, president of Toppan concluded, “During the past three years of joint work, we have been nurturing a strong collaboration as well as a highly sophisticated technical development capability. We believe this joint initiative will place IBM and Toppan Printing at the forefront of advanced photomask technology development, and thus will enable us to contribute to the technological innovation in the world’s semiconductor industry.”