Your chip in half the time?

GUEST OPINION: A project's commercial success depends on designers' ability to deliver silicon on time. That's why the industry recognizes the growing importance of time to results.

By Rajiv Maheshwary, Synopsys -- EDN, 7/9/2008

Is there something on your office wall that demands all of your time and all of your attention? Is it your chip schedule, by any chance? What if you could bring the tapeout forward just a little? What if you could compress the development time—or cut it in half, even?

Not only would such a drastic schedule reduction put you firmly in control of your project, but the economics of product development suggest that it would pay dividends also. Recent analysis conducted by Synopsys, and based on a number of conversations with engineering VPs, suggests that just a 10-week schedule delay can completely wipe out the profits of any product with a two-year lifecycle. Conversely, delivering product to market earlier than your competitors can generate very substantial profit-margin gains and accelerate time to revenue.

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According to our research, most IC companies take approximately 24 months to get a project from specification to product. Time to market has shrunk 12 months in the past 10 years. It's even worse news for product derivatives, which are typically introduced every 6 to 12 months. What's behind this? One thing is that as consumers we are eager to adopt new technologies. Just consider the time taken to reach mainstream use for the following technologies: TV: 13 years; cable TV: 10 years; Internet: five years; camera phone: three years. This compressed technology-adoption lifecycle impacts the design cycle, as does increasing competition. Consider the fact that more than 100 new cell-phone models are introduced each month. Which one will you buy? The pressure on design teams to deliver is growing.

So, back to your project schedule. Before we can think about cutting it, we need to understand what's driving it. According to our research, completing verification is still the No. 1 pain point that impacts schedule (see chart). Creating test plans, meeting coverage goals, and coping with mixed-signal and system validation all eat into valuable project time. Next on the list comes achieving design closure, a task that is still plagued by unpredictable iterations. Accommodating spec changes is another issue. Managing timing constraints can also delay tapeout by weeks. Ultimately it's the unpredictability of many of these tasks that is the real project killer.

The time spent actually running design tools typically takes up a quarter of the total project schedule. While improving tool performance is imperative, it's clear from the figure above that this alone is not going to double overall productivity. There are many other factors that we must take into account if we are going to achieve our productivity goals.

Elements of a productivity solution

Focusing on five key solution elements can help design teams move toward achieving 2x productivity. These elements are:

• Integrated design and verification platforms
• EDA tool runtime and capacity
• Access to quality internal and commercial IP
• Hardware platforms for pre-silicon software development
• Proven design and verification methodologies

Data from real customer projects demonstrate that each of these elements can mitigate project risk and accelerate time to results.

Using integrated platforms for design implementation and verification can give productivity a boost. For one thing, integration enables core technology to be shared between tools. If you can look ahead to more accurately predict the results of downstream design activity, you are less likely to need to iterate the design, which is one of the major design headaches in trying to achieve design closure. Sharing analysis engines between tools enables excellent correlation of results at different stages of the design flow.

Platform integration is also key to achieving high levels of automation, both within tasks and between tasks in the flow. Advanced design functions such as multicorner, multimode analysis accelerate design closure for timing and power, and are made possible by the high levels of automation within an integrated platform. On an ARM1176 core running at 664 MHz using 45-nm process technology, we were able to demonstrate a 7× improvement in time to results (14 days to two days) when a customer switched from a multivendor design flow to an integrated platform solution.

There are similar productivity benefits to be had from using an integrated platform for verification. By incorporating system-level, functional, and mixed-signal verification within a single solution, the overall verification task becomes far more efficient. With an integrated verification platform, the verification engineer can work at a high level of abstraction to achieve fast runtimes, and still perform detailed analysis of custom circuitry where appropriate.

Taking advantage of the latest hardware platforms is a must in order to achieve the best tool runtimes. The world is going multicore, and by using EDA applications written specifically for multicore computers, design teams are enjoying improved tool runtimes. Some customers are reporting 2× verification throughput thanks to these improvements.

We have seen that having access to a broad portfolio of prequalified commercial IP can cut the IP qualification schedule by 30% and reduce cost by 20%, as well as reduce silicon risk. The design team that delivered the world's first dual HDTV decoder chip reported that use of an IP-based assembly flow was 2.5× more productive than its previous approach. Good quality IP, including models that support both design and verification, is essential if optimal productivity improvements are to be achieved.

Software development has become a significant bottleneck for many chip projects, but there are solutions to help address this. For example, one wireless handset design team was able to use virtual platforms to start its firmware development four months before silicon became available, and improve its overall software development productivity by between 2× and 5×. FPGA prototyping is another valuable productivity aid, which helped a Wimax 802.16e startup design team shave six months off its overall project schedule while delivering first-time working silicon.

Use of proven methodologies within each solution element and across the key productivity-solution elements—IP, integrated design and verification platforms, improved tool runtimes and hardware platforms for pre-silicon software development—significantly and positively impacts the end result. For example, use of the verification processes described in the VMM (Verification Methodology Manual) enabled a virtualization chip design team to reduce development time by 50% compared with its previous approach.

Now more than ever, a project's commercial success is linked to designers' ability to deliver silicon on time. That's why the industry recognizes the growing importance of time to results for the design community, and why this focus will intensify going forward.

Adopting any of these productivity solutions decreases design time. But the real potential lies in implementing a comprehensive strategy that intelligently leverages all of these techniques. Such a productivity strategy, using today's most advanced tools and techniques, can reduce the time to design your chip by half¯a significant savings when considering today's short market windows.

Rajiv Maheshwary is the senior director of marketing in the Solutions Group at Synopsys, Inc.