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LP DDR2 DRAM momentum begins to build

The LP DDR2 specification is potentially important to mobile device designers, and also to developers of power-conscious servers, primarily because of its reduced operating voltages. However, the devil is in the implementation details.

By Ron Wilson, Executive Editor -- EDN, 7/25/2008

The JEDEC specification for the low-power DDR2 (LP DDR2) DRAM is likely to be published fairly soon, according to sources. But already at the Denali MemCon conference this week at least two vendors were discussing LP DDR2 products: a DRAM from Samsung, and a controller IP block from Denali. Previously, Elpida and Hynix have announced LP DDR2 devices.

The LP DDR2 specification is potentially important to mobile device designers, and also to developers of power-conscious servers, primarily because of its reduced operating voltages—as low as 1.2V for I/O and for the DRAM core—and reduced pin count. Both of these points reduce operating power. But there are additional features in the specification, some of them not yet revealed by the JEDEC Committee, that will also help with energy consumption. These may include additional power-down options. All of these power savings are to be concurrent with an increase in performance over LP DDR1, to a maximum I/O frequency of 533 MHz.

Samsung's LP DDR2 DRAM is stepping up to this goal in stages. The initial parts, in full production in 2009, will use 1.2V I/O and a 1.35V core. In 2010 Samsung will migrate to a design with a 1.2V core voltage, as the memory designers learn to stabilize the very analog goings-on in the DRAM core at the lower voltage. But Samsung director of marketing Mueez ud Deen said that the biggest problem the company anticipates in rolling out the parts is not on the DRAM side—it will be "gearing up the processor-vendor base to handle the new parts."

That will be a nontrivial problem, according to the team at Denali. There will be new operating modes to learn on the new parts, and that learning will be critical to the actual energy savings designers will see at the system level. You do automatically get some savings—up to 30% in the core and 40% in I/O, by Samsung's reckoning—from the lower operating voltage and reduced number of signal pins. But that is just the beginning of the power savings, according to Marc Greenberg, director of technology marketing at Denali.

"SOC designers are beginning now to get comfortable with voltage-frequency scaling to save energy," Greenberg said. "But you can't just turn down the voltage on a DRAM. Both the I/O and the core are very sensitive to voltage variations. So you have to save energy by shutting circuits down altogether.

"For that reason, low-power DRAMs are optimized for fast power-down and power-up operations," Greenberg continued. "The problem then is figuring out when you can safely power-down a memory channel or a DRAM chip, and what power-down mode you should use. A lot of variables go into that decision, particularly in an SOC, where multiple clients may be sharing a DRAM. It turns out that the memory controller is about the only place in the system that all those variables are available—the only block that can potentially tell if it is safe to shut the memory down. That fact is putting a premium on intelligence in the memory-controller design for LP DDR2."

There is another major issue with the LP DDR2 spec as well, one that vendors are approaching with a certain amount of caution. A multipin channel operating at 533 MHz with 1.2V signaling is a nontrivial design problem at the board level. It is at least at the outside edge of the signal-integrity capabilities of many OEMs. "What's worse," Greenberg observed, "is that LP DDR2 uses unterminated lines. They didn't want the terminations there consuming power. So we find that we are already doing some pretty significant signal-integrity consulting work with customers who are planning-out these 1.2V channels."

With challenges in getting high yield and high reliability out of the 1.2V DRAM cores, challenges using the new power-management modes effectively, and signal-integrity issues escalating to a new level, applying LP DDR2 parts in a system will be a demanding task, probably requiring joint effort by the DRAM, controller, and system vendors.