IBM, partners claim smallest SRAM memory cell

A precursor to more complex devices such as microprocessors, the SRAM cell leverages a conventional six-transistor design and has an area of 0.1-square-microns, which breaks the previous SRAM scaling barriers.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 8/18/2008

IBM Corp researchers in Yorktown Heights, NY along with development partners Advanced Micro Devices Inc (AMD), Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE) reported today that they have developed what they believe is the world’s first working 22-nm SRAM, built at IBM’s 300-mm research facility in Albany, NY.

A precursor to more complex devices such as microprocessors, the SRAM cell leverages a conventional six-transistor design and has an area of 0.1-square-microns, which breaks the previous SRAM scaling barriers, the companies explained.

The researchers said they achieved the breakthrough at CNSE of the University at Albany, State University of New York, which is believed to be the most advanced university based nanoelectronics research complex where IBM and its partners do much of their leading-edge semiconductor research.

“We are working at the ultimate edge of what is possible -- progressing toward advanced, next-generation semiconductor technologies. This new development is a critical achievement in the pursuit to continually drive miniaturization in microelectronics,” said Dr. T.C. Chen, VP of science and technology at IBM Research, in a statement.

This development is significant in that traditionally, an SRAM chip is made denser by shrinking its basic building block, often referred to as a cell. In this case, IBM and its partners explained that they optimized the SRAM cell design and circuit layout to improve stability and developed several novel fabrication processes in order to make the new SRAM cell possible, and used high-NA immersion lithography to print the pattern dimensions and densities, fabricating the parts in its 300-mm research environment.

Band edge high-K metal gate stacks, transistors with less than 25-nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts were key enablers of the SRAM cell, IBM said.

More details of the SRAM will be presented during the IEEE International Electron Devices technical meeting to be held in San Francisco in December.