Elpida leverages architecture to achieve chip shrink

Elpida’s chip size shrink was made possible by leveraging a new architecture on first-generation 65-nm process products, and estimates that costs for the shrunken version of 65-nm products will be approximately 20% less compared to first-generation products, the company explained.

By Ann Steffora Mutschler, Senior Editor -- Electronic News, 10/6/2008

By using a new architecture on first-generation 65-nm process products, Tokyo-based DRAM giant Elpida Memory Inc said today it has developed a shrunken version of its 1-gigabit DDR2 SDRAM that is meant to deliver 20% more chips from a single 300-mm wafer, which translates to a 60% increase in chips compared with wafers for a 70-nm process, with volume production to begin before the end of this year.

For more from EDN on Elpida, see: Capital spending: can it get worse? Micron rumored Qimonda buy 'likely to happen,' analyst says Elpida, Qimonda may set up joint manufacturing activities Hynix, Numonyx expand joint NAND development work Elpida, Chinese venture group to spend up to $5B on China DRAM plant Intel, Samsung, TI, Toshiba maintain top spots in IC Insights semi ranking Elpida will manufacture 300-mm NOR flash for Numonyx NEC, Elpida plan display driver IC joint venture

Production will be shared between its Hiroshima Plant, its Taiwan-based Rexchip joint venture and its manufacturing partner PSC, Elpida said.

Elpida also explained that the chip size shrink was made by leveraging a new architecture on first-generation 65-nm process products, and estimates that costs for the shrunken version of 65-nm products will be approximately 20% less compared to first-generation products.

Further, the Japanese DRAM giant said that as the migration to 50-nm process technology leads to higher wafer processing costs due to the need for capital expenditures, the company believes its new 65-nm process-based chip will be cost competitive with 50-nm products by DRAM competitors.

Also, Elpida said it has reached the final stage of developing a 50-nm process and plans to complete work next month, with volume production expected as early as late December, ahead of its earlier January-March 2009 timetable.

The migration to 50-nm products with a chip size of smaller than 40 square millimeters should further increase performance and lower costs by making it possible to improve productivity roughly 50% compared with the 65-nm shrunken version, Elpida said.

Finally, Elpida believes the chip shrink gives it flexibility to make capital spending decisions and choose manufacturing process composition in response to either prolonged sluggishness in the DRAM market or a relatively early recovery.