SAR (successive-approximation-register) ADCs (analog-to-digital converters) are playing an increasingly prominent role in the design of highly effective data-acquisition systems for automatic test equipment, instrumentation, spectrum analysis, and medical instruments. SAR ADCs make it possible to deliver high-accuracy, low-power products with excellent ac performance, such as SNR (signal-to-noise ratio) and THD (total harmonic distortion), as well as good dc performance.

For optimum SAR-ADC performance, the recommended driving circuit is an op amp in combination with an RC filter (Figure 1). Although this circuit commonly drives ADCs, it has the potential to create circuit-performance limitations. If you don’t properly select the input resistor, R_IN, and the input capacitor, C_IN, values, the circuit could produce ADC errors. Worse yet, it could cause the amplifier to become unstable. If you ignore the op-amp open-loop output impedance and UGBW (unity-gain bandwidth), you may run into amplifier-stability issues.

The optimized ADC-driver circuit in Figure 1 uses an op amp to separate the ADC from high-impedance signal sources. The following RC lowpass filter, R_IN and C_IN, performs functions going back to the op amp and forward to the ADC. R_IN keeps the amplifier stable by “isolating” the amplifier’s output stage from the capacitive load, C_IN. C_IN provides a nearly perfect input source to the ADC. This input source tracks the voltage of the input signal and charges the ADC’s input sampling capacitor, C_SH, during the converter’s acquisition time.

In evaluating the circuit in Figure 1, you can determine the guidelines and constraints for selecting the value of R_IN. The op amp’s open-loop output resistance, R_O, and the UGBW or the unity crossover frequency, f_U, as well as the value of C_IN, govern this issue (Reference 1 and Figure 2). After defining the design formulas for R_IN, you can determine the value of C_IN. The ADC’s acquisition time and input sample-and-hold capacitance, C_SH, as well as R_IN, influence the value of C_IN.

Once you understand how this circuit operates, you can establish the criteria for a stable system and define an appropriate design strategy. A proof of concept uses two sample circuits. The first is relatively stable; the second is marginally stable.

The ADC in Figure 1 cycles through two stages while converting the input signal to a digital representation. Initially, the converter must acquire the input signal. After acquiring the signal, the converter changes the sampled information, or “snapshot,” of the input signal to a digital representation. A critical part of this process is to obtain an accurate snapshot of the input signal. If this ADC-data-conversion process is to run smoothly, the driving amplifier must charge the input capacitor to the proper value and maintain stability during the ADC’s acquisition time.

You can determine the stability of an amplifier with a Bode plot, a tool that helps you approximate the magnitude of an amplifier’s open- and closed-loop-gain transfer functions. In Figure 2, the units along the Y axis describe the gain in decibels of the amplifier in Figure 1. The units along the X axis describe the frequency in log, hertz of the open- and closed-loop-gain curves.

If the closure rate of the closed- and open-loop-gain curves is greater than 20 dB/decade, the amplifier circuit will be marginally stable or completely unstable. For example, if the open-loop-gain curve, A_OL, is changing at –40 dB/decade, the amplifier circuit is unstable where the slope of the closed-loop-gain curve, A_CL, is zero at the intersection with the open-loop-gain curve.

You can evaluate the stability of the circuit in Figure 1 with the op amp’s open-loop-gain function, A_OL (Figure 2). The amplifier’s dc open-loop gain is 120 dB. At approximately 7 Hz (f₀), the op amp’s open-loop curve leaves 120 dB and progresses down at a rate of –20 dB/decade. As the frequency increases, this attenuation rate continues past 0 dB. The open-loop-gain curve, A_OL, crosses 0 dB at approximately 7 MHz (f_U). Because this curve represents a single-pole system, the crossover frequency, f_U, is equal to the amplifier’s UGBW. This plot represents a stable system because the closure rate of the closed- and open-loop-gain curve is 20 dB/decade.

Figure 3 provides an accurate picture of the amplifier’s performance minus the ADC’s impact. Introducing the external RC on the op amp’s output modifies the amplifier open-loop-gain curve.

When evaluating the amplifier’s open-loop-gain curve with R_IN and C_IN in the circuit, you need to include the effect of the amplifier’s open-loop output resistance, R_O. The combination of R_O, R_IN, and C_IN modifies the open-loop-response curve by introducing one pole, f_P (Equation 1), and one zero, f_Z (Equation 2). The values of R_O, R_IN, and C_IN determine the corner frequency of f_P. The values of R_IN and C_IN determine the corner frequency of the zero.

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In the interest of stability, the effects of f_Z must occur at a frequency lower than the intersect frequency of the open-loop- and closed-loop-gain curves (f_CL). Figure 4 illustrates a condition in which f_Z is higher than the open-loop/closed-loop-intersection frequency, f_CL. In this situation, the amplifier circuit is marginally stable, with a phase margin of less than 45°. For this circuit, marginal stability can occur if the closure rate between the open- and closed-loop-gain curves is greater than 20 dB/decade.

You can find the modified closed-loop bandwidth, f_CL, by using the amplifier UGBW, the open-loop gain at the pole frequency (f_P), and the modified open-loop gain at the zero frequency (f_Z). The following equations describe the curves in figure 2 and figure 3 and identify f_CL:

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The frequency distance between the pole and zero must be equal to or less than one decade. This requirement is necessary because the phase change from zero negates the phase changes that the pole initiates. Note that the pole formula (Equation 1) includes R_IN and R_O; the formula for zero (Equation 2) includes only R_IN. If the distance between the pole and zero exceeds one decade, the phase response will not “recover” in time, and the output of the circuit will show more ringing.

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Correct values of R_IN and C_IN

The primary purpose of capacitor C_IN is to charge the ADC’s input sampling capacitor, C_SH, during the ADC’s signal acquisition. With C_IN in the circuit, the amplifier should provide less than 5% of the charge to C_SH during signal acquisition, and C_IN provides more than 95% of the required charge. To ensure that C_IN provides most of the charge to the ADC’s input during acquisition, C_IN should be greater than or equal to 20 times C_SH (reference 2 and reference 3).

R_IN serves as the isolation resistor between the op amp and C_IN. R_IN assists in stabilizing the amplifier, but its secondary task is to ensure that the system can charge the input ADC capacitor in a timely fashion (Reference 3). The time-constant multiplier of this ADC acquisition time is K (Table 1). As a first step, with these two variables and C_IN,

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As a first step to optimization, look at the C_IN and op-amp characteristics. During op-amp production, internal components can vary. Capacitances can change by as much as ±15%. Additionally, the op-amp transistor’s transconductance can vary from ±5 to ±15%. So, if you are looking for a variation of f_U at 25°C with three times sigma, you can use ±20% as a good starting point.

It is good practice to use f_CL=f_U/2 and f_Z =f_CL/2 or f_Z=f_U/4 for good stability over different production lots. If these conditions are a concern, having G_Z equal to 6 dB or f_Z=f_CL/2 further stabilizes the system from production lot to production lot.

Using these gain and frequency points’ definitions, you can make decisions about the best values for R_IN and C_IN. If you define G_Z as equal to 3 dB, then 0 dB=3 dB–20×log(f_CL/f_Z) (Equation 5) or f_CL=1.41×f_Z(f_Z=f_CL/1.41). If you want G_Z=6 dB, then 0 dB=6 dB–20×log(f_CL/f_Z), or f_CL=2×f_Z(f_Z=f_CL/2).

This theory is a good start, but proof of concept completes the picture. Two sample circuits tie this theory to reality. These designs use the OPA364 as the op amp with a UGBW of 6.45 MHz and open-loop output resistance, R_O, of 110Ω. Both designs also use a 1500-pF capacitor for C_IN. The target closed-loop bandwidth, f_CL, in the design is f_U/2, or 3.23 MHz, and the target frequency of added zero is f_U/4, or 1.61 MHz.

Two conditions are observable using an R_IN of 66.5Ω (Design 1, the relatively stable circuit) and 15Ω (Design 2, the marginally stable circuit). You can then observe the effects of a small-signal step response at the test point, V_IN. The op amps are in a buffer configuration, with a 1V/V closed-loop gain. The second series of tests uses the ADS7886 for the SAR ADC.

In the first design, R_IN is 66.5Ω. Combining the effects of C_IN, R_IN, and R_O produces a pole frequency, f_P (Equation 1), at 601 kHz with an open-loop gain, G_P (Equation 3), of 20.6 dB. This combination of C_IN, R_IN, and R_O also produces a zero, f_Z (Equation 2), at 1.596 MHz with an open-loop gain, G_Z (Equation 4), of 3.65 dB. Figure 3 shows the system’s Bode plot. Figure 5 shows the response of V_IN when the noninverting input of the op-amp buffer sees a 280-mV-p-p, small-signal step response. The signal at V_IN is stable within 1 µsec. This condition is desirable for this SAR ADC.

In the second design, R_IN is 15Ω. With the values of R_IN, C_IN, and R_O, the pole frequency, f_P, is 849 kHz at an open-loop gain, G_P, of 17.6 dB. The zero frequency, f_Z, is 7.074 MHz with an open-loop gain, G_Z, of  –19.22 dB. Figure 4 shows the system’s Bode plot. Figure 6 shows the response of V_IN when the noninverting input of the op-amp buffer sees a 280-mV-p-p, small-signal step response.

This marginally stable test circuit generates an overshoot with ringing, which is undesirable. The ADS7886 produces an unstable and inaccurate result from the signal in Figure 6.

These measurements show how the system responds to an input step without the ADS7886 connected. You can expect similar results when the load changes with the ADS7886. Closing the ADS7886 sampling switch generates a kickback current. Adding the ADS7886 to the circuit makes it difficult to observe 12-bit-accurate changes with an oscilloscope. Therefore, you apply a new measurement technique.

The test begins with the addition of the ADS7886 to the circuit (Figure 1). This circuit applies a constant voltage at the noninverting input of the OPA364. Testing began with an ADS7886 acquisition time of 300 nsec and 4096 measurements; testing continued with an acquisition time of 60 nsec, again with 4096 measurements. The acquisition time continued to increase by increments of 60 nsec until the test was complete for both designs.

After collecting this data, calculations of sigma and mean values for every ADS7886 acquisition point yield the results in table 2 and table 3. In the tables, the top line identifies the additional acquisition for the ADS7886 beyond the initial acquisition time of 300 nsec from test to test. The far left column lists the output-data codes and the number of times these codes appear in the body of the table. The statistical summary of the body of both tables appears at the bottom.

The data shows that the stable design has a lower sigma and more consistent mean. The mean value of the unstable system has an error of more than 0.7 LSB, whereas the stable system has an error of less than 0.03 LSB.

Choosing the right op amp for the ADC is critical. Be sure to compare issues such as amplifier noise, bandwidth, and settling time to the ADC’s SNR, SFDR (spurious-free dynamic range), input impedance, and sampling time. The primary purposes of capacitor C_IN are to provide charge to the ADC’s input sampling capacitor, C_SH, during the ADC’s signal-acquisition time and to offload the amplifier from dynamic activity from the ADC. The proper design equation when determining C_IN is:

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