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XMEGA processor sports event system for deterministic performance with low power

By Robert Cravotta, Technical Editor -- EDN, 10/30/2008

Atmel’s 8/16-bit ATXMEGA A3B microcontroller combines an eight-channel event system with a four-channel DMA controller that simultaneously manage eight interperipheral signals and as many as four 64-Mbps data communication. The device accomplishes these tasks at 32 MHz without any CPU intervention and at a power draw of 12 mA, not including CPU activity. The event handler allows the system to avoid software-managed context switching and interrupt handling. An event consumes less than 10 nA, and event-response time is as fast as 31.25 nsec. The maximum guaranteed response time of an event is two clock cycles, or 62.5 nsec with a 32-MHz system clock.

The software-configurable XMEGA event system manages autonomous triggers for peripheral-to-peripheral interactions using timer/counter-compare-match-or-overflow, analog-comparator toggle, pin-change, ADC-complete-or-compare, and real-time-counter-overflow events. These events can trigger actions in other peripherals that include ADC or DAC conversion, input capture to time-stamp communication or ADC measurements, external frequency or pulse-width measurements, clocking of timer/counters, starting a DMA transaction, or changing a pin output.

The four-channel DMA controller can move data from a peripheral register to internal or external SRAM/SDRAM, between SRAM locations, and between peripheral registers. Each DMA channel can transmit 1 byte to 16 Mbytes in a single transaction, and each has individual priority, source, destination, trigger, and addressing modes. The device’s linear data-memory-address space and 24-bit auto increment/decrement and reload features in the DMA controller enable these autonomous data-transfer sizes.

The XMEGA has 32 general-purpose registers and supports 16- and 32-bit arithmetic. The CPU can feed two arbitrary registers from the register file to the ALU (arithmetic-logic unit), perform a requested operation, and write back the result to any register in a single cycle. XMEGA devices use the same AVR CPU as all other TinyAVR and MEGAAVR microcontrollers. All XMEGA microcontrollers are pin- and 100%-code-compatible.

The XMEGA A3B employs Atmel’s picoPower technology, which enables 100-nA current draw in sleep mode and maintains full SRAM retention and the ability to wake up from an I/O-pin change within 5 μsec. The on-chip real-time counter requires 500-nA current draw when operating from a 32.768-kHz crystal oscillator. The brown-out-detector and watchdog timer have a combined current consumption of 1 μA. The XMEGA A3B includes a battery-backup system. If the system loses power, it automatically switches the power source to the backup battery within 800 nsec to support continuous operation of the real-time clock and crystal oscillator. The system can detect crystal-oscillator failure and low battery-backup voltage to further protect the system without external components.

The XMEGA includes an on-chip AES (Advanced Encryption Standard) and DES (Data Encryption Standard) hardware-cryptographic engine. It can execute the AES algorithm in 375 clock cycles per 16-byte block to support 1-Mbps secure communication. The DES executes at 16 clock cycles per 8-byte block to support 2-Mbps and higher secure communication. XMEGA devices with the cryptographic engine are authorized for export to all countries except Cuba, Iran, Libya, North Korea, Syria, and Sudan (export-control classification no. 5A002A.1).

The free AVR Studio development tool supports all AVR microcontrollers. IAR Systems’ Embedded Workbench and the free GNU GCC compiler also support development for the XMEGA. Debugging tools include Atmel’s AVRone!, JTAGICE mkII, and the STK600 starter kit. These tools also support all other AVR and AVR32 UC3 products. Several XMEGA devices are available immediately with 64 to 256 kbytes of flash memory in 64- or 100-pin packages for $3.12 to $3.55 (10000).