Making ASICs gel

GUEST OPINION: The enormous complexity possible in ASICs today has had a damping effect on design starts. Many in the industry simply can’t afford to design the chips their customers want, and that their foundries can easily fabricate. We postulate a design flow that, by focusing on identifying the customer’s behavior-level requirements and mapping them onto a proven platform, reduces design complexity and breaks the logjam in ASIC designs.

By David Fritz, Silistix -- EDN, 11/18/2008

For years analysts have chronicled the worldwide decline of the ASIC business and projected the trend to continue into the foreseeable future. While many have speculated as to why this trend is inevitable and irreversible, these views do not comprehend fundamental shifts in the underlying dynamics that can reverse this trend. I postulate, completely against conventional wisdom, that this downward spiral is not inevitable but that it is, and must, be reversible.

Consider the established fact that an accelerating worldwide gap exists between the number of qualified engineers being produced and industry demand, and the skyrocketing complexity of chips as they race to take advantage of the "sea of gates" available at new process nodes. For the first time in history we can now manufacture chips of a complexity that surpasses what we can practically design. The prevailing notion that existing EDA tolls will carry the industry forward and track Moore's Law is beginning to crack under the stress. Unless the "next-great-thing" has already been invented, there must be another answer beyond continuing to do more of the same.

To understand my postulate, consider the ASIC business at a high level.

Your job is to produce an ASIC for your customer, and to do so at a profit. The conventional approach is to take a netlist from your customer and produce working silicon. In this model you would need to provide a fixed price quote that you must perform against in order to make a profit. Your value as an ASIC provider is in your experience of how to drive a design to working silicon faster and more cost effectively than your customer could do themselves.

But what assurances do you have that it's possible to produce working silicon from the delivered netlist and whatever requirements the customer might supply? You would try to understand the design before quoting, but if that's all it took, why would your services be needed at all. The truth is that you are betting on your ability to drive your tool flow to increase the likelihood of success when you nave no control over or insight into many of the variables that determine success. As a result, you either pad your quote making it less competitive, or you go back to your customer and ask for more money – neither of which is conducive to a healthy business.

It should be no surprise to anyone in the semiconductor industry what these variables determining success are; some combination of communications issues between functional blocks, top level timing closure, complex power reduction techniques, verification issues, latency problems, performance issues, and process variations. The problem isn't the existence of these variables but the impact of these variables is unknown and can't be discovered until huge amounts of effort are invested, only to be re-invested once a problem is discovered. The root of the problem is that existing methodologies entirely exclude the possibility of knowing if what is being specified can actually be built with a predictable amount of effort.

For the ASIC industry to once again gel, what is needed is a methodology that addresses these variables by bringing process-dependant issues and complex design and implementation decision capabilities to the very beginning of the process and not leaving them to be discovered only after investing huge efforts. In other words, we need to bring predictability to the entire architecture, design, and verification and implementation process. What will return the ASIC business to its former stature, and indeed reinvigorate the semiconductor industry as a whole, is a methodology that holistically comprehends how functional IP blocks communicate, what the system level requirements are, what the impacts are of latter stage design and implementation issues, and what the impacts of process corners and variability are on the design, following it from idea to silicon.

With this methodology in place, an alternate predictable approach to the ASIC business is available to the forward thinking. In this model, you extract your customer's high level requirements early in the engagement process. Through an iterative process you map the customer's requirements into something that you have a high degree of confidence can be efficiently built and provide a quote based on understanding of the variables that determine success. Though you are leveraging your design expertise and available resources to the maximum, you are also constantly pushing the boundaries of what can be done in a predictable fashion.

A pipedream you say? Think again. The solution exists today!

Author Information

David Fritz is the Chief Executive Officer at Silistix. Previously, he served as Vice President of Marketing and Business Development for ARC International where he focused on developing the Asian market. David was previously founder and president of Production Languages Corporation, a pioneer in configurable processor technology, where he was awarded a US patent covering fundamental processes related to configurable processors. Production Languages Corporation was subsequently acquired by ZiLOG in 1999, and he then became vice president of ZiLOG's Advanced Cores R & D and ZiLOG's Development Systems Group. He holds degrees in Mathematics and Computer Science from Manchester College, and began his career at Texas Instruments and DSC Communications.