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Through-silicon vias, oxide bonding accelerate 3D IC development

Stacked-die assemblies are moving beyond wirebonding for die-to-die interconnect. But are design tools ready for them?

By Ron Wilson, Executive Editor -- EDN, 12/1/2008

As the costs and challenges of process nodes below 65 nm grow clearer, chip architects are paying more attention to an alternative: 3D die integration. In addition to packing more components into the same footprint, stacking dice into three-dimensional assemblies offers the ability to use an optimized semiconductor process for each type of circuitry in the system, the ability to exploit commodity pricing for blocks such as large memory arrays, and the ability to achieve high levels of integration without forcing the entire design into a very advanced—and very expensive—process.

Stack-die arrangements are already widely used, of course, in cell phone handsets. And they are spreading into other areas, leveraging the substantial learning-curve work done by the handset industry. But these designs mostly rely on conventionally-designed dice, with conventional I/O pads, stacked up and wire-bonded together. While achieving greater density and allowing mixing of digital, analog, and memory dice, this approach forgoes the real promise of true 3D integration: the ability to treat all the blocks in the assembly in the same placement and routing hierarchy, regardless of their physical location in the stack.

Two quite different recent announcements advance toward that ideal. In one, Applied Materials has announced a new etch system called Silvia (pictured) intended to create through-silicon vias to support 3D interconnect without wirebonding. In another, IC assembly house Ziptronix has discussed incorporation of a nickel-metal-metal interface into its direct oxide bonding technology for wafer-to-wafer interconnect.

The Applied Materials work addresses production issues in a technique that has been attracting considerable research—drilling vias deep into a wafer, then lapping the back of the wafer until the bottoms of the vias are exposed to create a through-wafer connection from the Metal-1 layer on the top to a metal-bump layer on the bottom. Much interesting work has been done on this process at, for example, IMEC.

In principle, through-silicon vias (TSVs) would allow a natural extension of the interconnect hierarchy to include links between dice. Inter-die links would have different impedance characteristics and different routing rules, but they would permit very high connection counts and would be designed with existing routing and timing tools, unlike wirebond interconnects, which are so different from on-die interconnect that they must be treated as I/Os. For instance, using TSVs, a multibank SRAM array on a memory die could be directly wired into a wide bus on a digital die, without the need for multiplexing and interface electronics. This would allow almost arbitrarily wide memory structures, and would substantially reduce SRAM latency and transfer energy.

But creating the TSVs has been a challenge. According to Applied product marketing manager Brad Eaton, aspect ratios for TSVs can exceed 25 to 1. Yet the vias must have diameters as small as 1 micron in some processes, and must have extremely smooth sides. Edge roughness in the via can trap residue, interfere with proper filling, and eventually lead to electrical and reliability problems.

To meet these problems, Applied has called upon technology originally developed for the enormous aspect ratios (nearly 100:1) required for Qimonda's trench-capacitor DRAM process. Using an etch process that alternates silicon etch and polymer deposition in rapid succession—essentially digging deeper and then lining the wall of the hole to protect it from lateral etching—the Silvia tool is able to reduce the scalloping on the edge of deep vias to about 25 nm, while achieving etch times short enough for production equipment.

This addresses only one of the challenges in the 3D integration process, of course. At the wafer level, there are still the problems of thinning the wafer until the bottoms of the vias are exposed, forming electrical contacts on the back of the wafer over the via openings, and handling these super-thin wafers without breaking them.

This is where recent work at Ziptronix may come in. The company has considerable IP in the area of low-temperature oxide-to-oxide bonding. Essentially, the company puts two wafers face-to-face and holds them there until the oxide layers on top of the wafers fuse. This creates a strong, planar, molecular-level mechanical bond between the wafers, allowing them to be diced after bonding. Vias brought to the surface of the oxide, if they line up on the two wafers, come into contact during the bonding process.

Except for a detail. A native oxide layer forms over the top of the via during normal processing. To eliminate that layer, Ziptronix has developed a way of interposing a nickel layer before bringing the wafers together. The nickel breaks the native oxide over the via metal, allowing the vias on the two wafers to fuse. This creates a single via that runs from the interconnect stack on one wafer up through the oxide layer between the wafers and into the interconnect stack on the other wafer.

The primary limit on the density of these vias appears to be alignment accuracy during the direct oxide bonding process. Ziptronix spokesman Chris Sanders says that the company has demonstrated 1.5-micron alignment, and that equipment exists that should be able to achieve 0.25-micron alignment.

Today, the Ziptronix technology seems to be used primarily for applications such as backside imaging arrays for handset cameras. In this case, the imaging wafer is thinned so that light can pass through the back of the wafer into the photodiode array, and then the imaging wafer is flipped and bonded, face-to-face, to the wafer containing the digital electronics. This application requires only a single bond between two wafers. But in principle, Sanders says, direct oxide bonding can be used to create large stacks of wafers for more ambitious 3D structures.