Figure 1 depicts one corner of an FPGA package. The figure shows the balls on the bottom side of the FPGA as they would appear from underneath the package. You could never see this view in a real application. In this photo, portions of the PCB (printed-circuit board) appear transparent to reveal the vias plunging down to lower layers in the board.

The FPGA package contains a large number of controlled-impedance traces. Those traces connect the die to the balls on the underside of the package. The traces are laid out on a tiny BGA (ball-grid-array) substrate inside the FPGA package. The substrate incorporates multiple solid power and ground planes, much like a normal PCB.

Drawn with pink and blue highlights, a differential-signal pair exits the FPGA on two adjacent balls. The differential pair is routed on PCB Layer 1. The dielectric beneath Layer 1 is transparent, so you can see the bottom side of the two traces as they lead away from the package.

The path through the balls is a transition region. From the tiny traces inside the BGA package, the differential signal flows down through the balls to the lower world of much larger Layer 1 traces on the PCB. As your signal passes through the transition region, the differential impedance of that area depends mostly on the geometry of the two balls at the point of exit, the two traces, and their relation to the nearest underlying solid reference plane in the PCB.

The configuration in Figure 1 is the most favorable exit strategy for a differential pair in a BGA package. The entire path is compact and symmetric with respect to the surrounding planes. With the differential-signal traces on Layer 1, no drilled holes or vias complicate the situation.

Signal transitions occur wherever your signal passes through a package body, a connector, or a pair of vias. Whatever the geometry of your design, if you keep the entire transition region smaller than the rise and fall time of the driver, you can average together the details of that geometry into a simple approximation for the transition region. That approximation is commonly represented as one short section of differential transmission line with characteristic impedance, Z₁, different from the characteristic impedance of the surrounding transmission structure, Z₀. Because you can average the properties of compact structures over their extent, you can compensate for imperfections at one point within the transition by counterbalancing imperfections at other points within the transition region.

For example, if the ball spacing is too large, driving Z₁ too high, compensate by increasing the size of the BGA solder pads, thus adding capacitance and driving Z₁ back down to the correct average value. Inserting nearby compensation to fix problems elsewhere within the transition region is the secret to successful transition design. It works only when the overall transition delay is less than about one-tenth of the signal rise or fall time.

If your transition delay exceeds one-tenth of the signal rise or fall time, then you must break the transition down into subsections, each small enough to satisfy the one-tenth rule, and then separately compensate the average impedance within each subsection.

To help you gauge the difficulty of transition design, Table 1 computes the total delay of a few common transitions. In each case, the table shows the minimum rise/fall time for which the structure acts in a simple, lumped-element manner, and you can easily tweak it to obtain optimum performance.