DPGAs (digitally programmable-gain amplifiers) are handy signal-processing components whenever ADCs must acquire signals with a wide dynamic range. Without the ability to accommodate input-signal amplitude to match and efficiently use ADC span, low-level inputs may not be digitized with adequate resolution, and high-level inputs may overrange the ADC and be lost altogether.

Currently available DPGA designs typically incorporate a multiplying DAC into an op-amp-feedback loop, so that the input code to the multiplying DAC sets the amplifier’s closed-loop gain. Several available monolithic DPGAs, such as Linear Technology’s LTC6910 and National Semiconductor’s LMP8100, employ this topology. But the DPGA’s digital-gain-control bits are sometimes inconvenient to provide, and these devices’ output span may be inadequate, for example, to interface to ±10V ADC-input spans. Also, the resolution of these devices’ available gain settings is usually coarse—for example, 2-to-1 per gain step—and their power consumption is sometimes large. In contrast, this Design Idea describes a new DPGA that employs the concept of the divergent-exponential curve.

No waveform is simpler or more familiar than the e^–t/RC-convergent exponential—the asymptotic discharge to zero of an elementary RC circuit initially charged to the input voltage, V_IN, in which V=V_IN/2 at t=T=log_e(2)RC, V_IN/4 at t=2T, V_IN/8 at 3T, and so forth. Less familiar, but just as simple, is the behavior of the same RC topology when you replace R with an active circuit that synthesizes a negative resistance (Figure 1). Replacing R with –R makes the RC time constant negative: –RC and the waveform function yield the divergent exponential, V_IN×e^+t/RC. Then, instead of converging to zero, the waveform diverges theoretically to infinity, and V=2V_IN at t=T, 4V_IN at 2T, 8V_IN at 3T, and so forth. Therefore, no matter how small the input voltage might be, you can amplify it as much as you desire to any voltage by simply waiting the right amount of time=t=log₂(V/V_IN)T after starting the negative discharge.

The divergent-exponential and negative time constants are the core concepts of the DENT (divergent-exponential-negative-time-constant) DPGA topology (Figure 2). When the amplify/-control bit goes to logic one, the two-times-noninverting gain of the op-amp follower creates a negative time constant: –(R+1R_ON)(C+C_STRAY)=–14.4 µsec, where R_ON is the on-resistance of the CMOS switch, and C_STRAY is the parasitic capacitance surrounding C (Figure 3). It also creates a diverging exponential: V_OUT(t)=V_IN×2^{(t/10 µsec+1)}. Thus, gain=2^{(t/10 µsec+1)}. The 1-µsec timing resolution in the amplify-control bit provides 1.07-to-1=0.6 dB=33 steps/decade gain-programming resolution. Figure 4 graphs the voltage gain versus the time elapsed since the track/amplify-logic transition.

Unlike monolithic PGAs, DENT uses discrete components, such as op amps and switches, so it can easily accommodate parameters such as I/O-voltage spans—negative inputs and 10V amplitudes—by choosing appropriate parts and power supplies. The accuracy and repeatability of the timing of exponential generation, ADC sampling, and RC-time-constant stability limit the practical performance of the amplifier in gain-programming accuracy and jitter. In the sample circuit, with T=14.4 µsec, 1 nsec of amplify-timing error or jitter equates to 0.007% of gain-programming error. Fortunately, the near ubiquity of programmable timer/counter hardware in popular microcontroller and data-acquisition peripherals usually makes the digital generation of a precisely repeatable amplify/track control an easy matter. On the analog side, possibilities exist for self-calibration algorithms that preserve gain-setting accuracy and relax RC-component-precision requirements, but they lie beyond the scope of this Design Idea.