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Low-power wireless performance starts with CMOS elegance
The IC Insider delves into an ISM transceiver implemented in standard CMOS, revealing that interference-free operation in this crowded swath of spectrum begins with attention to layout details.
By Randy Torrance, Chipworks -- EDN, 1/5/2009
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For example, many types of applications—alarm and security systems, automatic meter-reading systems, wireless sensor networks, and other home and building automation products—use the ISM (industrial, scientific and medical) and SRD (short range device) frequency bands at 315, 433, 868, and 915 MHz. To operate in these crowded slices of spectrum, a device must tolerate interference from other ISM equipment and maintain low enough power that it does not interfere with that equipment. In this installment of The IC Insider, we put a transceiver that operates in these bands under the microscope to see how IC designers accomplish this delicate balancing act.
Texas Instruments' Chipcon CC1101 (TI acquired Chipcon in 2006) is a full sub-1-GHz transceiver including all the circuitry required for receiving and demodulating the RF signal, and for modulating and transmitting this same signal. The part features a low-IF receiver. The IC first amplifies the received RF signal using an LNA (low-noise amplifier) and then downconverts the signal in quadrature (I and Q) to an IF (intermediate frequency). ADCs then digitize the I/Q signals. The transceiver performs AGC (automatic gain control), fine channel filtering, and demodulation bit/packet synchronization digitally.
The CC1101's transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer includes a pair of completely on-chip LC VCOs and a 90° phase shifter for generating the I and Q local oscillator signals to the downconversion mixers in receive mode.
The device includes an on-chip regulator for the digital supply. There is also a selection of bias voltage and current generators deriving their input from a bandgap reference voltage circuit. A large on-chip test system appears to allow quite a variety of test modes. Also included on-chip are clock synthesizers based on a crystal oscillator and an SPI serial interface.
The CC1101RTK is manufactured in a four-metal, one poly, 0.18-micron CMOS process and mounted in a 20-pin QLP package. The design also features an interesting assortment of resistors and capacitors. For this article we have chosen to concentrate on two intriguing circuits: the VCO used in the RF frequency synthesizer and the bandgap voltage reference.
VCO
The frequency synthesizer is a key circuit in any RF system. This circuit needs to generate a very accurate, stable, low-jitter, high-speed clock. On this chip the challenge is even greater because the circuit must be implemented in a standard 0.18-micron CMOS process. The CC1101's frequency synthesizer is built as an "all-on-chip" PLL (phase locked loop). The frequency synthesizer requires two VCOs in order to cover the full range of frequencies the applications demand. The extracted schematic in Figure 1 shows the core of one of these VCO systems.
This is a typical tank oscillator including fixed capacitors, a programmable capacitor, an inductor, cross-coupled PMOS and NMOS gain elements, a programmable current source for the tail current, and a bit of digital logic.
Manufacturers first placed inductors on standard CMOS chips just a few years ago. An inductor needs a low inherent resistance to allow for a high Q-factor. On a chip, it is hard to achieve that low resistance due to the thin metals usually used to allow for narrow pitches (typically less than 1 micron thick). Nevertheless, Chipcon implemented inductors for its VCOs in this standard 0.18-micron CMOS process. The designers used the two top levels of metal, metal 3 and 4, to implement these inductors. The inductors are the circular structures visible in Figures 2 and 3.
The IC implements programmable capacitance for the VCO with a standard design. Switches, implemented with NAND gates, selectively insert binary-weighted capacitors into the design. The capacitors are implemented as standard unity-gate-oxide capacitors, as shown in the view of the polysilicon layer in Figure 4.
In this figure one can see six pairs of binary-weighted capacitors (the sixth pair on the right using two columns of capacitors) and, on the left, the fixed capacitors for the VCO. The layout is a typical symmetrical arrangement, with lots of space around the devices. But what we find most interesting is the metal-3 interconnect for these devices. As shown in Figure 5, this interconnect uses tapered metal lines.
This is a very rare find. Few ICs require this amount of attention to detail in the layout. Evidently Chipcon felt it was worth it in this case. These nicely matched tapered wires must be used to ensure the best matching possible across all these capacitors. This layout may be used to maintain good matching of parasitic resistances, capacitances, inductances, or, in fact, all three.
The final piece of interesting layout involves the cross-coupled NMOS and PMOS elements in the VCO. Although we expected to see nothing more than a standard transistor layout, we found something more surprising. Figure 6 shows the layout of one of the cross-coupled NMOS transistors on the polysilicon layer.
As seen in the schematic of Figure 1, this is a four-fingered 2.5-micron/0.18-micron transistor. The transistor is visible in the center of this layout. It is interesting to see the two separate guard rings around this device. The inner ring fully encloses the transistor with an N+ diffusion used as a substrate contact. The outer ring fully encloses the device with a P+ guard ring connected to VDD. This outer ring is a full 6 microns from the transistor—a huge distance in a 0.18-micron process. Finally, three unconnected polysilicon strips can be seen on each side of the transistor.
Bandgap voltage reference
Last month I wrote about the interesting bandgap voltage reference in the Invensense IDG-300 gyroscope IC (see "MEMS-based inertial sensor is not your grandfather's gyroscope"). The Chipcon CC1101 has an equally well designed bandgap reference. Figure 7 shows the extracted schematic: a typical bandgap reference circuit.
The bandgap core, with the ratioed NPN transistors and currents, resides in the center of this schematic. The error amplifier appears on the left, and a startup circuit and cascode bias appear on the right.
Once again, Chipcon has worked hard to ensure good matching and accuracy. The cascode bias ensures accurate current matching between the ratioed NPNs. In fact, both NPNs use the same current, rather than the more usual approach of ratioing the currents. This results in a large ratio for the NPNs (a ratio of 22 to 1, in fact), but ensures better current matching. Also of note is that the error amplifier input devices are NPNs, ensuring accurate matching between the critical amplifier input devices and the ratioed NPNs. And once again, the layout is very nicely done, as you can see in Figure 8.
The input NPNs of the error amplifier, highlighted in this image, are symmetrically embedded in the ratioed NPN array. The single device of the right branch is between the two input NPN devices, and the 22 NPNs of the left branch include all the surrounding transistors. This layout once again provides very good matching between all these devices.
These are just a few of the many interesting circuits on the Chipcon CC1101. In extracting the entire analog portion of this chip, we were impressed with the design style and the attention to detail. As these few examples show, Chipcon put a lot of effort into ensuring the best matching possible in the design and layout.
Author information
Randy Torrance leads the Circuit Analysis team for the Technical Intelligence group at Chipworks. During 22 years in the technology industry he has held senior technical and management positions in the IC design and electronic systems areas. He holds bachelor's and master's degrees in Electrical Engineering from the University of Waterloo.
