Many system engineers assume that a differential-clock source should drive just one chip. If a system design requires driving two DDR-memory chips, however, the design would inevitably need a differential-clock buffer. This Design Idea describes a circuit that drives two DDR chips without a clock-source buffer yet does not sacrifice much of the signal integrity.

The cost-saving nature of an SOC (system-on-chip) design dictates the need for fewer pins. Such designs typically have only one pair of differential signals available for external-memory-chip connection. When the system design requires more than one DDR chip, designers typically use a clock buffer.

Figure 1 shows an SOC with an embedded DDR controller, which connects the SOC’s differential clock to two DDR-memory chips. Differential signals CLK and CLK– from SOC chip IC₁ connect to series resistors R₁ and R₂, respectively. The differential traces then connect to DDR-memory chips IC₂ and IC₃ with a 120Ω termination resistor near IC₂.

Figure 2 shows the equivalent PCB (printed-circuit-board) layout. The PCB comprises a four-layer FR4 material with a ground plane under differential lines CLK and CLK–. The CLK and CLK– signals are routed close to each other and pass through series resistors R₁ and R₂, which are also placed close to each other, to provide proper termination. The closely spaced differential signals connect to IC₂ with the 120Ω termination resistor, R₃. The bottom-layer traces are necessary to connect the differential signals to IC₃. The total length of the differential pair is approximately 2.5 in. from the SOC chip to the DDR chips.

The SOC provides DDR differential clocking. With various values for R₁, R₂, and R₃, the best results occur when R₁ and R₂ are 0Ω and R₃ is unconnected. Figures 3 through 7 show various waveforms for the signals.