Researchers at Helsinki University of Technology have demonstrated that single-walled carbon- nanotube FETs using hafnium-oxide as a gate dielectric can exhibit some of the characteristics of a flash-memory cell, including 100-nsec write/erase times and 10,000-cycle endurance. But the retention time of the devices, 40 hours, is too short for practical application.

The team fabricated the transistors on a silicon substrate. The researchers used atomic-layer deposition to put a 20-nm layer of hafnium-oxide dielectric over the silicon. Then, the team deposited random segments of nanotubes onto the dielectric layer using a solution containing 1.2- to 1.5-nm-wide, 100- to 360-nm-long nanotubes.

With an atomic-force microscope, the team then identified nanotube segments that settled into the correct orientation for the experiment. The researchers installed palladium source and drain structures on the ends of the selected nanotubes and passivated the assembly's surface with another layer of hafnium-oxide.

The palladium dots act as the source and drain contacts of the transistor, the nanotube is the channel, and the silicon substrate is the gate electrode. Applying a gate-to-source voltage causes charge-trapping in the dielectric layer, influencing the conductivity of the nanotube. The researchers can detect the level of charge-trapping in the transistor by measuring source-to-drain current for an applied source-to-drain voltage.

They can improve the retention time of the device by adding an oxide layer, but they have not yet addressed the problems of accurate placement or proper orientation of nanotubes on the substrate or the variations in nanotube electrical behavior.