Ceva’s Ceva-XC DSP core employs the company’s Ceva-X architecture to support 3.5 and 4G wireless designs. The new architecture accommodates one, two, or four vector-communication units alongside a single general computational unit to provide hardware support for as many as 64 simultaneous 16×16-bit MAC (multiply/accumulate) operations or 128 16×8-bit MAC operations when using all four vector units. Each vector unit is a 256-bit SIMD (single-instruction/multiple-data) engine using a three-way VLIW (very-long-instruction-word) architecture that supports as many as three parallel instructions, with each instruction operating on 256-bit registers.

Each engine can incorporate optional instruction sets to better balance between performance and cost to support transmitter functions, floating-point operations, and the CORDIC (coordinate-rotation-digital-computer) algorithm. Additional advanced hardware includes support for MIMO (multiple-input/multiple-output) detectors; channel estimation; and bit-chain processing for interleavers, scramblers, and FEC (forward-error-correction) encoders.

The execution units combine with the memory subsystem to enable a software implementation for LTE (long-term-evolution) Class 5 or WiMax (worldwide-interoperability-for-microwave-access) II designs that must support a downlink data rate of 300 Mbps with 4×4 MIMO. The memory subsystem employs AXI (advanced-extensible-interface) master and slave system buses that are configurable between 64- and 128-bit widths, and it includes an APB (advanced-peripheral-bus) 3 interface to support slow devices.

The memory subsystem supports caches; tightly coupled memories; and interfaces for emulation, profiling, and real-time trace modules. It supports optional EEC (extended error correction) for memory error detection and correction. The DMA (direct-memory-access) engine supports 2-D transfers that can operate in background data transfers and data-rate-matching modes.