This [problem] is not just a financial matter. If you have one chip going into production every 18 months, your production engineers and operations managers aren’t getting enough experience to stay on their learning curves. That’s not good for the company or for the engineers. You need to shift these activities to someone who can achieve economies of scale.

We are basically an aggregator, but maybe we are best known as a fabless-ASIC company. Because we handle lots of designs per month, we very quickly get up the learning curve on back-end design of new nodes. Instead of each new design’s being a new experience, we are able to develop a fairly automated methodology at a new node. We are doing mostly 40- and 45-nm designs, for instance. At this stage, we are tuning the methodology to a manufacturing experience: working on yield and reliability optimization, where we can and cannot compromise with the foundry on design rules—things that come from experience.

But customers have taken us beyond just the design space. Because we are such a large customer to the foundries we work with, we have economies of scale and influence, and we are also skilled in managing product life cycles. As fabless companies understand this point, they see the possibility of changing the business model.

Basically, we can offer to take over responsibility for production on an existing product, deliver the chips to you at the price you have today, and meet the goals on your cost-reduction road map. And we can make money doing that.

In addition to looking at outsourcing operations, are you seeing the fabless-semi companies and system houses looking for other economies, such as postponing designs?

We are seeing every possible form of cash conservation. Companies are taking designs to RTL [register-transfer-level] freeze and then shelving them. They are delaying tape-outs. They are cutting wafer orders. The paradox of all this is that we as an industry are managing our resources better than we ever have before, but we are still seeing the worst situation.

The good news is that, because of all the attention the industry has paid to inventories since the Internet bubble, we may be in a better position than in the past. Companies we talk to expect to purge their inventories in one to three quarters, not two years.

And design doesn’t come to a stop. Companies are still conducting R&D, and they are still doing algorithm development. One thing that might change, though, is the shocking amount of overdesign that has been common in the industry. Design teams may have used 65 nm for a design that would have worked just fine in 90 nm. They might have specified 600 MHz just for head room when the requirements were only 450 MHz. We may see a lot of that overdesign evaporating now as companies try to reduce their NRE [nonrecurring-expense] levels.

Reducing NRE—that must be music to the ears of FPGA companies.

You know, this is the fourth major recession since the introduction of FPGAs, and their use model still hasn’t changed. They are still a small fraction of the size of the ASIC/SOC [application-specific-integrated-circuit/system-on-chip] business. I think perhaps some people have misunderstood that [idea] because chip-design starts have been dropping, but that drop has been primarily because, with increased integration, one SOC will do what 10 ASICs used to do. The drop is not primarily because of FPGAs’ displacement of ASICs.

Reality is that, today, if you can reduce the cost of a chip by 50 cents, that is justification enough to replace it in the bill of materials. In that kind of environment, you are not going to pay a huge premium for an FPGA.

Do you see the recession accelerating dispersal of design teams around the world?

No. Design teams will continue to outsource portions of the design, but we maintain that at a certain level of complexity, proximity of the lead engineers to each other and to the customer is absolutely vital. Dispersing tasks to outlying teams works only when there will be only low interactivity with the remote team and little or no customer involvement in that portion of the design.