News and New Products

Customizable microcontroller, $75,000 NRE costs target 10,000-unit applications

By Robert Cravotta, Technical Editor -- EDN, 4/1/2009

Atmel’s AT91CAP7L standard-product microcontroller has as many as 200,000 gates of MCPF (metal-programmable-cell fabric) that you can use to implement proprietary customer IP (intellectual property), hardware accelerators, additional processor cores, or peripherals. The CAP7L relies on the company’s second-generation MPCF-II technology to reduce to $75,000 the NRE (nonrecurring-engineering) costs of implementing 200,000 gates of proprietary custom IP with an ARM7 core. For applications that target as few as 10,000 units, this combination results in a fully amortized unit cost of $18, including NRE costs and IP licensing. The original MPCF technology, which Atmel announced in 2007, uses six metal layers, and five via layers for the MP (metal-programmable)-library-cell configuration and interconnect. The new MPCF-II technology uses a new via-programmable-cell library that trades density for cost and supports configuration and routing of the chip using three metal layers and three via layers. This approach reduces the number of masks you need to modify from 12 with the first-generation MPCF to six with the new version and cuts the NRE costs by 50%. Prototypes are available within 10 weeks of receiving the final gate-level netlist, and production quantities are available within 12 weeks. CAP7E microcontrollers with built-in FPGA interface are available now for $9.50 (10,000), and CAP7L customizable microcontrollers are available now for $5.50 (50,000).

The MP block comprises about 15% of the CAP7L die area. The remaining 85% of the die is predefined, consisting of an ARM7 core with a four-layer AHB (advanced high-performance bus) and 22-channel peripheral-DMA controller; a USB (universal-serial-bus) device; an SPI (serial-peripheral-interface) master and slave; two USARTs; three 16-bit timer/counters; an eight-channel, 10-bit ADC; 160 kbytes of SRAM; and a system controller, including interrupt, power-control, and supervisory functions. The MP block sports two AHB masters and two AHB slaves, 14 APB (advanced-peripheral-bus) slaves, and 32-bit programmable I/O that you can hardware-select to share I/O. An on-chip priority-interrupt controller provides as many as 13 encoded interrupts and two additional unencoded interrupts for DMA transfers.

The design flow for the CAP7L is the same as it would be for an FPGA-plus-microcontroller or ASIC implementation. You initially develop the design using an Altera or Xilinx FPGA and an ARM7 microcontroller. You develop the HDL (hardware-description-language) code for any custom IP using standard, vendor-specific or third-party FPGA-design tools. Once it verifies the design, Atmel needs only the RTL (register-transfer-level) netlist to implement in the MP block on the CAP7L. Atmel provides the CAP7E ARM7-based microcontroller with direct FPGA interfaces. The interface on the CAP7E affords the FPGA direct access to the AHB and peripheral-DMA controller on the CAP7L. Atmel also provides FPGA logic that decodes and encodes the bus traffic that flows between the FPGA and the CAP7E microcontroller. The logic blocks inside the FPGA connect to the CAP7E through the AHB-master and -slave channels. You can use the CAP7E-plus-FPGA implementation for early-market-testing and proof-of-concept purposes before migrating to the CAP7L.

In addition to providing the ARM core, Atmel has a library of license- and royalty-free IP that the company has fully verified and tested in the CAP7L MP block. Atmel’s free IP includes a USART supporting RS-232, RS-485, ISO (International Organization for Standardization) 7816, and IRDA (Infrared Data Assocation) standards; an SSC (serial-synchronous controller); TDM (time-domain multiplexing); I²S (inter-IC sound); an AC (audio-codec) 97 controller; component specification Version 2.3; two-wire master and slave interfaces; SPI; an SD (secure-digital)-card/MMC (multimedia-card) host controller; a CAN (controller-area-network) 2.0B-plus-eight mailbox; 32 parallel I/Os; a timer/counter; PWM (pulse-width modulation); the 133-MHz TDES (triple-data-encryption standard); the 128-, 196-, and 256-MHz AES (advanced encryption standard); the SHA (secure hash algorithm); an AHB-to-APB bridge; an external-bus interface; an external static-RAM/flash controller; an ECC (error-correcting-code) controller for NAND flash; an SDRAM controller; and a ZBT (zero-bus-turnaround) RAM controller.