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Innovating out of the downturn
GUEST OPINION: If history is any indicator, innovation, not the business cycle, will pull the semiconductor industry out of recession. But this time young, innovative companies jumping on advanced processes may play a disproportionate role.
By Dr. Mark Liu, TSMC -- EDN, 4/23/2009
The world economy and the semiconductor industry have entered what Alan Greenspan described as the “perfect economic storm.” That is to say, we are in an economic spiral where the credit crunch feeds an already deepening recession. To complicate matters, this perfect storm has now been swept into a global economic hurricane.
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The prospects in front of the semiconductor industry today are at best bleak. The World Bank has pegged its growth forecast for the global economy at 0.9% for this year. The weakened outlook will be for the developed countries, such as the United States, Japan, and the European Union (EU), whose overall economy is expected to contract 0.1%, while developing economies are expected to register growth of about 4.5%.
Yet, there is good news on the horizon. For it seems that, at its darkest hour, the semiconductor industry is at its creative best by innovating its way out of the downturn and into the next growth phase. Despite the doom and gloom that characterizes today’s news, there is every reason to believe that history will repeat itself. The next generation of process technologies is available today to empower the next wave of innovative applications.
The semiconductor industry has not escaped the downturn. TSMC has forecast a 30% decline for the semiconductor industry this year. The smartest people in the forecasting industry are struggling to find common ground for their estimates. Candidly, no one really knows how this will shake out.
Innovating out of the downturn
Many expect that semiconductor consumption will grow in the emerging markets. We also expect that technology and innovation will be found in the United States, Europe, and Japan. Not too surprisingly, it is these mature markets that are at the leading edge when it comes to demanding the latest and greatest in functionality or the newest electronic gadgets. This is where the semiconductor industry will innovate its way out of the downturn.
Going back to the early 1990s, semiconductor manufacturing process technology improvements have, according to VLSI Research Inc., helped drive new product introductions (Figure 1). In 1992, the Windows operating system coincided with the introduction of 0.50-micron process technology. Developments in broadband were built on the 0.13-micron process that was available for production in 2001.
In past downturns, it was IDMs (integrated device manufacturers) who set the pace for innovation. But this time, there will be new business models to lead the pack. In 2009, it is the fabless semiconductor industry, its supply chain constituents, and its foundry partners who are playing major roles in the next recovery and who have put the infrastructure in place for the industry to innovate again.
IDMs will continue to play a significant role in fostering new products. But keeping in mind that the fabless segment accounted for 68% of TSMC’s fourth-quarter 2008 revenue—a ratio that has moved only slightly one direction or the other quarter on quarter—it is clear that the fabless semiconductor industry and its foundry partners will drive the next turn around.
So where are the new application areas that will drive the semiconductor industry out of the downturn? Not surprisingly, it will be the global consumer, probably motivated by the familiar “wow” factor, who will lead the semiconductor market out of its doldrums. From a demographic perspective, it will more than likely be the teens and pre-teens who will be the major influencers. Viewed from a perspective of new products built on advanced technologies, we see mobile devices, graphics applications, gaming platforms, and more powerful computing engines leading the charge. Interesting, too, will be a brand-new generation of applications driven by the time-to-market efficiency and robust design flexibility of the next generation FPGAs (field-programmable gate arrays).
A second wave of products that will most likely emerge toward the end of next year could include devices such RDD-read channel chips, network processors, CAM (content-access-memory) devices, camcorder upgrades, and new and innovative improvements to DTV.
Behind many of these new applications will be one of the most advanced available technologies: TSMC’s 40-nm process technology (Figure 2). TSMC’s 40-nm General Purpose (G) process and 40-nm Low Power (LP) process were announced in March 2008 and opened for volume production in November. The new processes address the faster time to market, investment optimization, and product differentiation required to move new, feature-rich products to market.
“TSMC’s 40-nm technology will be one of the enablers for the next generation of storage products that LSI is designing,” says Hai Wang, LSI Logic vice president of Global Sourcing and Manufacturing Technologies. “The power savings and performance improvements all add up to significant competitive advantages for our global customer base.”
The 40G process targets performance-driven applications, including CPUs, GPUs (graphic processing units), game consoles, networking, FPGAs, hard disc drives, and other devices. The 40LP process targets low-power applications, including cellular baseband, application processors, and portable consumer and wireless connectivity devices.
TSMC’s 40G and 40LP processes passed process qualification, reaching “first wafers out” status as planned and completed product qualification in October when first customer wafers entered production. As with every TSMC process node, the 40G and 40LP processes offer a full range of mixed-signal and RF options along with embedded memory to support a broad range of analog/RF-intensive and memory-rich applications.
"From storage devices to handheld units, 40 nm has enabled significant improvements in performance and power reduction required by our customers," said Dr. Albert Wu, vice president of operations at Marvell. "This process supports our mission to drive the next generation of consumer, mobile, and enterprise applications."
TSMC's 40G and 40LP processes offer designers up to a 2.35 times raw gate density improvement over the 65-nm node. The 40G process is up to 30% faster than TSMC’s 65-nm GP process at the same leakage rate, or up to 70% lower leakage at the same speed. In addition, it provides up to 45% lower active power than the 65GP process. The 40LP process provides up to 46% lower leakage and up to 50% lower active power than TSMC’s 65LP at the same speed. It also features the smallest SRAM cell size, 0.242um2, and macro size in production today.
Both TSMC’s 40G and 40LP are supported by a comprehensive IP portfolio that includes foundation IP such as standard cells, SRAM compilers, general-purpose I/Os, and electrical fuses and specialty IP that includes DDR2/3, LPDDR2, PCI-express, USB2.0, HDMI, MIPI, and ARM cores.
Supporting the process technology rollout is TSMC’s Open Innovation Platform (Figure 3). This is a platform for semiconductor design and manufacture innovation, hosted by TSMC, open to all its customers and ecosystem partners. The platform is supported by the Active Accuracy Assurance (AAA) initiative and driven through TSMC, enabling building blocks and interfaces.
The company’s AAA initiative enables designers to capture the maximum benefits of advanced technologies by providing the most accurate models and by reducing the overlapping guard bands in the design chain. It helps reduce implementation risk and improves time to market by defining a set of quality standards for IP, EDA tools, and other ecosystem services.
The Open Innovation Platform is a framework for a set of separate but interdependent programs that share a common core. The core’s key components are TSMC’s process technology, ecosystem interface, and the AAA program. Through this framework, TSMC will expand and enhance its existing design alliance programs and create new programs to stimulate customer and ecosystem innovation.
Incorporated into the Open Innovation Platform is Reference Flow 9.0. Reference Flow 9.0, a production-proven design infrastructure for 40-nm processes, includes a number of innovative techniques for power reduction, enhanced timing, statistical design, and DFM (design for manufacturing). It also allows designers considering 45-nm design rules to transparently target their designs to 40-nm processes without explicitly dealing with a multitude of scaling factors.
Taken together, Open Innovation Platform and Reference Flow 9.0 support innovation-driven companies by providing the design infrastructure to speed time to market, reduce waste, and enhance return on investment.
Although the 2009 outlook is bleak, it still seems more than likely that the semiconductor industry will, one more time, innovate its way out of the current downturn. The key imponderable may be when.
But when “when” comes, it also seems probable that a strong cast of fabless players will, this time, join the IDMs in the march forward. The foundries in general, and TSMC in particular, will play a major role in supporting the next generation of products.
The good news is this: With the availability of 40-nm process technology and support through the Open Innovation Platform, the infrastructure is in place to re-invigorate the semiconductor industry and to help innovate its way out of the current downturn.
| Author Information |
| Dr. Mark Liu is senior vice president, Advanced Technology Business, TSMC. |
