News and New Products

Memcon panel explores readiness of DDR3

Chips are shipping, but questions remain about the ramp of the new DRAM standard.

By Ron Wilson, Executive Editor -- EDN, 6/29/2009

DDR3 DRAM is upon us, whether or not we—and it—are entirely ready. That appeared to be the consensus of a panel of memory vendors and industry experts at last week's Denali Memcon conference.

The one thing all the panelists agreed on is that DDR3 is real, it's shipping, and there will be a transition to it, just as there has been a transition to every other major DRAM standard in the past. "We already see a major increase in use by customers," affirmed Arun Kamat of Hynix. "We are now in production with competitive parts, and the test infrastructure for high-speed, low-voltage chips is in place."

The anticipated rapid ramp will be driven by both supply and demand, the vendors on the panel suggested. "I believe you will see the DDR3 parts cross over the cost per Mbit of DDR2 in Q4 or Q1," said Sylvie Kadivar of Samsung.

But the transition will not be without its issues. "DDR3 can significantly reduce the cost of ownership in newly designed platforms," Kamat said. "But it is not a plug-in replacement for DDR2 in existing designs." In fact, one questioner from the audience asked if DDR3 were not a complete paradigm shift from DDR2, pointing out that the fly-by architecture, requiring termination on the DIMM, pretty much limited DDR3 to one DIMM per channel.

Industry luminary Bill Gervasi answered that in fact the change to fly-by would be a major transition. "The unbuffered solution now has its troubles," he said. "Adding a register helps, but that increases cost." Gervasi said that, recognizing the issues with the new architecture, standards groups are looking at yet another new alternative—the Load-Reduction DIMM—to address the problem without what he described as the power blow-out of the Fully-Buffered DIMM design. "I think you will see notebooks moving to registered designs, and servers eventually adopting the Load-Reduction DIMM," he projected.

Another innovation Gervasi pointed to should actually help with adoption by minimizing the differences between parts from different vendors. "DDR3 uses an external calibration resistor and a calibration sequence," he said. "This should allow one board design to adapt to the differences between parts."

But Gervasi also pointed to potential problems. "The big risk now is fragmentation," he warned. "We are already looking at lowering the operating voltage below the standard 1.5V, simply because the power dissipation is so high. I think we could end up with vendors trying to maintain both speed and voltage bins. At some point, these will cease to be commodity parts."

Later Kadivar added to this point. "We think there will be an impact from the growing importance of netbook computers. Netbooks, with their small main memory, will actually have lower cost using DDR2. This is likely to cause further fragmentation, but we don't really know how much, or for how long. Eventually, even the Netbooks should come to a tipping point."

Gervasi pointed out that at 1.5V, DDR3 DRAMs create something like three times the power density of the most efficient DDR2 chips. This has caused systems vendors to push hard for a lower-voltage standard. Kadivar said, "I expect to see the reality of a 1.35V spec, and to see adoption of that voltage for servers in 2010."

Kamat added that scaling even below 1.35V was possible in the next process node, approximately 40 nm. But Denali's Marc Greenberg added that this could in itself create further compatibility problems, especially because even the 1.35V spec is not yet published. Gervasi said that in reality, because of the growing fragmentation in operating voltages new systems would need to be designed to sense the voltage requirements of the individual chip and adapt to them.

In addition the panel discussed some of the system architecture issues DDR3 faces. There is no question that the new parts offer a significant increase in raw bandwidth. Kadivar said that Samsung expected to have 1333-MHz parts in production next year. But Rambus' Michael Ching warned that raw bandwidth wasn't the direction in which the industry is moving.

"It's all about multicore," Ching said. "There is a real question whether we will have enough performance from the memory system in a multicore, thread-rich environment. In order to exploit faster DRAMs, we must look at thread-aware scheduling, and the whole issue of system efficiency."

Greenberg added a similar systems-level concern. "It's clear that DDR3 will be adapted for servers and PCs, just based on the cost per bit," he said. "In the past, embedded designs have followed the PC market to get the lower memory costs. But each generation has been more difficult to use than the last. At some point, the parts may be too much trouble for embedded designers."

Asked about how DDR3 would work in multicore systems, Ching said that in the near-term, it would suffice. "But if you look at smaller desktop systems, you will only have one bank of DRAMs. That means that until the software people figure out how to really adapt to multicore computing, you are going to have lots of threads contending for that one interface."

Greenberg added "the real villain here is t_rc—the latency to change banks in the array. What it comes down to is if you want performance out of these memory chips, you must intelligently schedule the commands you send to them.

"We need to explore how to map software execution efficiently into the memory," Greenberg continued. "So far, only the video guys have really worked this out."

Unfortunately, embedded designs in particular are making that a harder job. "Take a look at what's happening in cache architectures," interjected Gervasi. "These days you are getting incredibly high hit rates in the caches. That means the accesses that do go through to the DRAM are very random. And that, at the end of the day, means that systems designers will care a lot more about latency than they will about bandwidth."

But don't expect the DRAM industry to respond with anything different. Kamat pointed out that users, no matter what they asked for, were in reality reluctant to pay any premium at all for a special feature. That means that the part that soonest achieves the highest volume will be used almost exclusively, no matter what hoops it forces DRAM-controller designers to jump through.

So DDR3 is on the rails, not to be diverted. And it is likely to be a cost and performance win for servers and PCs, though the issues about DIMM design and operating voltage are far from settled. But in the embedded world, the picture is far from clear.