News and New Products

Design and test combine to speed yield learning

By Rick Nelson, Editor-in-Chief -- EDN, 7/8/2009

Verigy has introduced its Yield Learning Solution, which integrates on-tester, real-time capture and analysis of electrical failures on complex SOC (system-on-chip) devices. The product combines preanalysis modules on the Verigy V93000 SOC-test platform, including a design-centric analysis and visualization tool set. The Yield Learning Solution comprises the V93000 scalable test platform plus the Triage Fault Locator and YieldVision software-tool sets for failure-data capture and yield analysis. Triage provides on-tester fault localization and includes an on-tester sampling engine; YieldVision supports offline data analysis.

The scalable architecture of the V93000 allows for complete integration with the Yield Learning Solution. The Triage software’s proprietary algorithms enable efficient data processing, and the YieldVision analysis and visualization tools reduce the time required to diagnose problems. By seamlessly linking electrical test with physical-layout data, the tools allow fast localization of the root cause physical defects.

Diagnosing problems in nanometer-level-device design and manufacture is becoming more challenging, which makes it essential to close the loop between design, fabrication, and test, says Colin Ritchie, vice president of marketing for DFX (design-for-test, manufacture, or yield) products at Verigy. Verigy’s Yield Learning Solution addresses the design/fab matching that is essential for a successful business. He notes that design-for-manufacturability problems, which can result from lithography-unfriendly design or failure to adequately follow increasingly restrictive design rules. The inability to quickly isolate and fix such problems, he says, can lead to billions of dollars in lost annual revenue, citing VLSI Research figures.

Ritchie notes that traditional approaches to yield diagnosis can require many days to identify design problems that lead to yield loss—such iterative approaches often require retest of failed devices plus a sequence of fault-simulation and layout extraction to physically locate faults. The process is not only time-consuming, but also can generate terabytes of data. In contrast, says Ritchie, Verigy’s on-tester approach generates only kilobytes of data and delivers results in minutes.

The Yield Learning Solution efficiently links test back into both design and the fab, providing logic bit maps for both stuck-at and difficult-to-detect timing faults in scan chains and logic. The Yield Learning Solution provides both the accuracy necessary for the lab and the high throughput necessary for production—critical for both new-product introduction and ongoing manufacturing monitoring. Ritchie says that Triage can perform on-tester localization of blocked scan chains and hold-time faults while performing on-tester characterization. YieldVision, he says, “speaks the language of the designer and the language of the fab,” providing diagnosis at the wafer, die, and component level.

Ritchie cites customer results indicating a four-week acceleration in time to market, an increase in entitlement yield of as much as to 6%, and a tenfold reduction in the number of wavers required to reach entitlement yield.