Feature

Implementing power factor correction with frequency clamp critical conduction mode

An innovative power factor correction design, frequency clamp critical conduction mode, clamps the frequency with a near-unity power factor while keeping the simple control scheme of a critical conduction mode design.

By Patrick Wang, ON Semiconductor -- EDN, 8/19/2009

Introduction

There's an increasing need for high-efficiency power conversion for a wide range of applications. Among the several available power factor correction (PFC) solutions, the critical conduction mode (CrM) PFC is a preferred method, especially for lower-power applications, because of its simpler control scheme. However, the design will have problems caused by the wide operating frequency range. One simple solution is to limit the maximum operating frequency, with the accompanying drawback of increased total harmonic distortion (THD). As will be shown in this article, an innovative PFC solution, frequency clamp critical conduction mode (FCCrM), clamps the frequency with a near-unity power factor while maintaining the benefit of CrM PFC.

The CrM PFC topology and the improvement

A boost topology offers the simplest option for PFC. Different schemes, such as continuous conduction mode (CCM) and critical conduction mode (CrM), are available to control the instantaneous value of the inductor current in order to achieve the power factor correction. Among these solutions, the CrM PFC is the most popular because it requires a simpler control scheme. Each cycle starts as soon as the core is reset completely. The t_rr of the boost diode doesn't contribute to switching losses; hence, a boost diode with lower speed and additionally lower forward voltage drop is a good and cost-effective choice to achieve good efficiency. Meanwhile, due to the natural oscillation between the inductor and the parasitic capacitor seen from the power switch, the voltage on the power switch will go down naturally, which will reduce the turn-on losses further.

However, CrM PFC suffers from limitations such as the higher rms current and wide operating frequency over a line cycle and different loading conditions. The drawback caused by the higher rms current limits the power range it can handle. The drawback caused by wide operating frequency is the risk of generating interference, higher switching losses, highly dissipative snubbing networks, and lower power factor ratio at light load.

An alternative way to solve the pain caused by wide operating frequency is to limit the maximum frequency. However, this method will be accompanied by distorted input current.

As an example, consider a 270W PFC design with a target output voltage of 390V and assume a 50-kHz operating frequency with a peak sinusoidal input of 100V ac. The PFC inductor can be calculated based on the following equation:

 (eq. 1)

Choose 250 µH for its nominal value. Figure 1 shows the input current and frequency at 230V ac. The operating frequency at a peak of 230V ac input is 65 kHz, but near the zero crossing it is about 400 kHz! This high frequency might cause some trouble, as mentioned in the beginning of this article.

A simple solution is to clamp the maximum frequency. But it will accompany a higher THD of input current. Figure 2 compares the calculated average input current with and without the frequency limitation in ½ line cycle by assuming no phase shift between voltage and current. With the frequency limitation, it operates at CrM near the peak of sinusoidal input and at DCM as frequency is limited where the input current is distorted. This distorted input current will worsen the power factor (PF) and THD. When the operating frequency is closer to the frequency limitation—for example, a higher input line or the lower loading—PF and THD will be further worsened.

Figure 3 shows the inductor current in one cycle and illustrates the reason why the input current is distorted if only the maximum frequency is limited. t₁ is the duration when power MOSFET turns on, t₂ is when boost diode turns on, and t₃ is the dead time when neither power MOSFET nor boost diode turns on. The average input current of one cycle is:

at DCM         (eq. 2)

where D_cycle is defined as the duty ratio of duration with current flowing in the inductor to the total period. It is denoted that the pure CrM operation is when t₃ is zero (that is, T = t₁ + t₂):

 at CrM        (eq. 3)

Compare Equation 2 with Equation 3, as t₁ of the CrM PFC is constant for a given line and load condition, the average input current at DCM would be lower than CrM (Reference 1). The longer t₃ is, the lower the average input current is. This is why the input current is distorted as the frequency is limited.

An innovative solution that captures the benefits of CrM and eliminates the drawback of wide operating frequency without the drawback of THD is frequency clamp critical conduction mode control. The idea to solve the distorted input current is to increase the power MOSFET on time based on the t₃ information as the frequency is limited.

Look at equations 2 and 3 again. Define t₁ as equal to some value, k, operating at CrM in some certain input and output condition. The idea of this solution is to modify t₁ at DCM to:

            (eq. 4)

Re-formulate Equation 4 as follows:

 at DCM          (eq. 5)

By controlling t₁ depending on the ratio of dead time (t₃) to duration with current flowing in inductor (t₁ + t₂), the average input current will be the same as the pure CrM PFC.

Figure 4 compares the input current in one cycle in three different ways: pure CrM, CrM with frequency limitation, and the proposed FCCrM. Again, define the power MOSFET on time in the pure CrM as equal to k in this certain cycle:

 (eq. 6)

 (eq. 7)

where D is defined as  and , which are the same in the certain cycle no matter whether it is CrM or DCM.

• The first graph is the current in pure CrM operation without frequency limitation. The average current in one cycle is equal to .
• The second graph is CrM with frequency limitation. Define the duty ratio of duration with current flowing in the inductor to the total period:

           (eq. 8)

Because the power MOSFET on time is the same as the one in pure CrM operation, T could be performed as:

      (eq. 9)

The average current in one cycle could be calculated as:

(eq. 10)

which is less than the pure CrM operation (that is, the input current is reduced and, hence, distorted).

• The third graph is the proposed FCCrM; its period is the same as the second graph:

but the power MOSFET on time (t₁) is expanded:

         (eq. 11)

Hence, the peak current is increased:

        (eq. 12)

and t₂ is expanded to . Naturally, that is influenced by the inductance and its voltage drop. In the end, the average current in one cycle is calculated as:

 (eq. 13)

It is exactly equal to the average input current in the pure CrM operation shown in the first graph. The average input current is well compensated.

The NCP1601 and NCP1605 from ON Semiconductor offer this patented control architecture that maintains PFC through the mode transitions and delivers superior performance compared with alternative approaches (Reference 2). These two devices also keep the flexibility of modifying the maximum frequency and, hence, the operation mode, depending on input and output conditions.

To optimize the efficiency, it is recommended to make it operate at CrM at full load and low line conditions and operate at DCM at the other conditions. Hence, the peak currents at low line are maintained at the same level as the pure CrM, but the maximum frequency is significantly reduced, easing the filtering burden. Another crucial benefit of reducing the switching frequency is that it helps in reducing light-load or no-load power consumption to meet various regulatory standards. Figure 5 shows the efficiency result on 270W applications by clamping the maximum frequency at 100 kHz.