Consider an application that needs a series of pulses to indicate position in which the lack of a pulse "indexes" the count. To achieve that goal, the application uses a rotating, 36-tooth sprocket with one missing tooth. Rotational speed ranges from 500 to 7000 rpm. The mechanism uses an inductive pickup to sense the sprocket's teeth. With one of the sprocket's 36 teeth missing, the detector senses 35 pulses, and then a pulse disappears.

Unfortunately, the mechanism frequently breaks down or simply breaks apart. Because the application uses this wheel just to trick the computer by simulating an operating engine, the application's designers replaced the rotating gear with a simulator circuit (Figure 1). Given the rotational speed and number of teeth, the maximum pulse frequency is 7000/60×36, or 4200 Hz. The circuit works well from single stepping to more than 1 MHz before starting to break down. The maximum frequency depends on the logic family and construction methods you use.

Figure 2 and Figure 3 show the outputs running at 100 Hz and 1 MHz, respectively. At power-up, capacitor C₁ remains the same, which forces RST on IC_3A low. That action puts the D flip-flop into a known state. As C₁ charges through R₁, the voltage at the power reset falls, letting clock pulses set IC_3A's outputs. You must keep the small value for the C₁/R₁ combination if you use a high input frequency with a low count rate. As Figure 3 shows, the desired count must exceed the duration of the power reset. The values in Figure 1 provide a time of approximately 0.66×1 kΩ (the value of R₁)×1 nF (the value of C₁), or 0.66 µsec, leaving a minimum count of approximately three at 1 MHz.

For the clock signal, the circuit uses a sine-wave signal with an amplitude of 5 to 10V from the system. The clock signal goes through R₃ to D₄ and IC_1A to produce a 5V square-wave signal. The signal goes to counter IC₂ and to one input of AND gate IC_4B. With the other input of IC_4B coming from IC_3A's QN output, which is high from power reset at start-up, the input-pulse train passes through IC_4B, which simulates sprocket teeth at the sensor. Resistors R₆ and R₇ halve the clock-signal amplitude just to make the graphics clear at "signal in." Diodes D₁, D₂, and D₃ pull up to 5V through R₂ and form an AND gate to select the desired count. Counter IC₂'s outputs are binary, so, for a 36-tooth sprocket with one missing tooth, outputs Q0, Q1, and Q5 correspond to 1+2+32=35.

You can produce any count as high as 128 by adding the appropriate diodes on the Q outputs on IC₂. In other words, you need to generate one missing pulse of 36 to simulate the 36-tooth sprocket. Thus, you select a count of 35; the circuit automatically adds a count of one due to the one-clock delay of the counter. Because you reset IC₂ at power-up, all outputs are low, keeping the D input of IC_3A low, with a count of zero.

As clock pulses continue into IC₂ and when outputs Q0, Q1, and Q5 are all high, with a count of 35, IC_3A's D pin pulls high through R₂. On the next clock pulse, the Q output of IC_3A goes high and the QN output goes low, stopping the pulses from passing through IC_4B. This action indicates the missing tooth and produces the sense condition (the missing pulses in figure 2 and figure 3). Meanwhile, the Q output of IC_3A's output goes high, yielding a single detect pulse at IC_4C through R₄ and R₅. On the next clock pulse, with IC_3A's Q output high, IC₂ resets logic zero and is ready for the next count cycle. R₄ and R₅ halve the clock signal just to make the graphics clear at "detect."

The 4024 is an eight-stage binary-ripple counter. You can replace it with a 4040 counter to achieve a count of 2048, and you can cascade counters to get longer counts or delays. The 4040's pinout differs from that of the 4024, but their operation is identical. Some systems have an extra tooth instead of a missing tooth, and some have multiple missing teeth at odd locations around the sprocket, all waiting for replacement by this simple circuit.