Designers who use today’s large FPGAs on their PCBs (printed-circuit boards) face an increasing problem: handling the pinout and board tracking around the packages of these programmable devices. The FPGAs have large pinouts; they offer considerable flexibility in allocation of pins to internal logic functions but also have complex rules that you must follow when doing so.

FPGA designers typically accomplish this task with minimal knowledge of the connectivity of those pins to other packages on the PCB. Other engineers develop the overall circuit functions, connecting the FPGA to processors, memory, and other packages. The job of creating the PCB layout falls to yet other engineers, who must find escape routes for all the signal groups that emerge from the FPGA and route them to other packages. Those engineers must also account for features such as wide memory buses and fast signal lines.

To address these problems, Cadence has incorporated into its Allegro and OrCAD products software from Taray . The Taray software provides automated assistance in the FPGA-pin-allocation step, yielding a correct-by-construction process. The process, automated placement-aware FPGA-pin-I/O-assignment synthesis, gives the software knowledge of the pin-allocation rules for Xilinx and Altera FPGAs and of the connectivity of the logic function in the FPGAs to other packages.

Large FPGAs contain so much logic that it is difficult to represent their functions in an understandable form on one diagram, so engineers view different functions on different pages and lose sight of the bigger picture. The Taray tool tracks that information; it also allows you to make a generic placement of packages on a “canvas” when performing initial PCB design, and it yields a global view of connectivity and connection density. It further avoids manual errors in the pin-allocation step.

The offering is applicable whether you are designing an FPGA-based board as a final product or building an ASIC prototype in which the logic of the target device is divided among many complex FPGAs. Using the Taray/Allegro tool greatly simplifies such designs because the process that fragments the logic onto the FPGAs has no knowledge of placement or layout. With the new software, you can automate pin assignment across all of the FPGAs in one step.

The ability to quickly view an optimized placement for any given logic architecture also permits you to explore cost-versus-performance trade-offs at the board-design level. Under the Cadence PCB-tool brands, the software is available for the Version 16.2 release as OrCAD FPGA System Planner or Allegro FPGA System Planner L, XL, and GXL tiers, and it integrates tightly with OrCAD Capture, OrCAD PCB Designer, Allegro Design Entry HDL (hardware-design language), and Allegro PCB Design products. Taray also continues to sell its tool offering, 7Circuits, as a stand-alone product.

This article originally appeared May 20, 2009 in EDN Europe, please click here to view the article.