Fujitsu Microelectronics recently announced a 3.0-to-SATA (serial-advanced-technology-attachment)-bridge chip. The company intends the device to act as a connection between a USB (Universal Serial Bus) 3.0 cable and a SATA external-storage device. It incorporates an AES (Advanced Encryption Standard) engine—critical to many external-media applications—and Fujitsu claims that the chip can support 300-Mbyte/sec throughput with flow-through encryption/decryption.

The device includes USB 3.0 Revision 1.0 and 2.0 PHY (physical)- and link-layer blocks and has 3-Gbps SATA Gen 2i PHY and link layers. Structurally, the chip includes an internal bus for data movement, the AES engine, and an unspecified 32-bit microprocessor core with attendant SRAM. The CPU’s job is primarily system-control functions within the chip, such as initialization, dispatching tasks to the AES engine, and handling the intervention-required bits of the two link-layer protocols. The RAM is for code and data storage for the CPU rather than for buffering, according to Davy Yoshida, Fujitsu’s director of business development. The chip also includes an SPI (serial-peripheral-interface) port to an external serial-flash chip for boot-loading of code and some general-purpose I/O pins for status LEDs and other functions.

The chip requires both 1.2 and 3.3V supplies and typically consumes 550 mW. That requirement means that a bus-powered interface with a local regulator to step the USB supply pin down to the required voltages would eat up most of the allowed 900 mA during operation without passing any power on to the mass-storage device. So interfaces using the chip will require an external power supply, probably one that the storage device furnishes. Further, according to Fujitsu, the chip’s USB I/O pins do not tolerate high voltage, so they may require external protection circuitry to comply with the letter of the 3.0 specification about tolerating shorts to the power pin.

Fujitsu is looking at applications in both automotive infotainment and consumer electronics. So don’t be surprised to see the company’s PHY surface soon in some additional bridge chips, and perhaps in 40-nm form, in forthcoming consumer and automotive SOCs (systems on chips). For more on this development, click here.