Feature

Specify an external reference clock to improve SERDES performance

Various serial data standards require different clock specifications.

By Shawn Logan, LSI Corp -- EDN, 10/21/2009

The technical merits and economic benefits of high-speed serial data transmission on a circuit board or between neighboring circuit boards have led to the development of many high-speed serial transmission standards. Hence, most communication-based ASICs contain SERDES (serializer/deserializer) macrocells designed to provide compliance to a set of standard specifications.

SERDES macrocells require a timing reference, known as a reference clock. Both the ASIC and board designer are faced with the task of defining an appropriate reference clock source and a reference clock vendor. Translating the timing reference requirements for a specific SERDES macrocell to a set of specifications for an external reference clock is not a trivial task. Since SERDES reference clock requirements are not standardized, the requirements for a macrocell may be significantly different between SERDES vendors.

This article discusses a methodology to determine an ASIC reference clock requirement based on the serial standard as well as the SERDES topology. The goal is to allow the designer to understand the impact of reference clock performance on the ability of the ASIC to comply with its required serial data standard. The designer can then specify an optimum external reference clock that meets the SERDES performance requirements and provides a cost-effective solution.

A common SERDES macrocell has receiver input buffers and transmit output buffers contained within the SERDES macrocell boundary (Figure 1). However, for some SERDES, the input or output buffers of the ASIC serve as the standards-compliant interfaces. Central to the receiver and transmitter blocks of the SERDES macrocell is a clock-multiplying unit (CMU). An external reference clock provides a time base for the receive and transmit channels as well as the ASIC. The ASIC may include an integral divider between the external reference clock input and the SERDES reference clock input if the frequency of the external reference clock is greater than that required by the macrocell.

The CMU of the macrocell consists of an analog or digital phase-locked loop (Figure 2). The control loop consists of a voltage-controlled oscillator (VCO), a set of feedback dividers that provide a total feedback divider of value N, a phase detector (PD), and an analog or digital loop filter. The phase detector may also contain a frequency detector. The block is assumed to contain the required interface to the loop filter. It may contain a feed-forward divider (M).

The CMU phase-locked loop has a closed-loop transfer function that relates the phase response of its output signal "PD feedback clock" to the phase of its input signal "PD reference clock." The typical response forms a lowpass filter with some phase peaking dependent on the choice of phase-locked loop parameter values (Figure 3).

Since the CMU of a SERDES may support multiple serial data standards, the feedback divider and other parameters are programmable. The phase transfer function and its –3-dB bandwidth are application dependent. An example illustrates the impact of an application change on the transfer function.

The Broadcom BCM8706 contains a SERDES to convert between the XAUI (10 Gigabit Media Independent Interface) data rate of 3.125 Gbs and the IEEE 802.3ap rate of 10.3125 Gbs. The datasheet specifies an external reference clock input frequency of either 25 MHz or 156.25 MHz. With a 25-MHz external reference clock rate, you set the SERDES feedforward divider to 1, and a 25-MHz signal serves as the input PD reference clock. With the phase detector operating with 25-MHz input clocks, the –3-dB closed-loop bandwidth is limited since the phase detector produces an error signal every 40 ns. If you increase the reference clock frequency to 156.25 MHz, the feedback divider is decreased by a factor of 6.25, and the phase detector reports phase differences every 6.4 ns. This change in response time may be viewed as an increase in the –3-dB bandwidth of the transfer function.

The SERDES transmitter

Within each transmit channel of the SERDES, the time base from the CMU directly affects the quality of the SERDES serial output data. The transmitter does not possess an internal phase-locked loop; hence, the phase variations present on the clock it receives from the CMU will also appear on the high-speed serial data stream it produces.

Standards govern the electrical requirements of the transmit output data stream and include a set of transmitter jitter requirements. The jitter requirements differ for the various standards, but each standard usually provides a maximum total jitter (TJ) requirement and a maximum deterministic jitter (DJ) requirement within the total jitter requirement.

To measure the transmit jitter, the output phase noise of the transmitted data is passed through a filter specified by the standard. In the most general case, the filter consists of a lower –3-dB and an upper –3-dB frequency and forms a bandpass filter. Many specifications do not provide a limit for the maximum random jitter on the transmitted output waveform. However, you may estimate its maximum rms value (σ) for a particular bit error rate (BER) by assuming that its peak-to-peak value at a specific bit error rate combines arithmetically with the peak-to-peak deterministic jitter to form the total peak-to-peak output jitter. Using the transmit jitter limits for various standards (Table 1 and references 1–5), it is possible to calculate the maximum value of the random rms jitter component for a bit error rate objective of 10^–12, which corresponds to a peak-to-peak random jitter distribution of 14σ (Table 2).

The transmitter serialization process typically consists of the IC sampling the parallel data at the macrocell parallel data input terminals and synchronizing the data with increasing higher clock frequencies. In some SERDES, a clock governs a final data multiplexing operation at one-half the data rate. Its internal logic, multiplexing operations, and amplifier bandwidths contribute deterministic jitter to the serial data signal. However, the component of random phase variation at the serial output data stream is dominated by the random jitter of its time base. Hence, the random phase variation of the serial output data is dominated by the random jitter of the CMU output clock. For frequencies above the CMU bandwidth, the random phase noise variations of components within the CMU phase-locked loop dominate. To determine compliance with the specific serial data standard, the transmitter output phase noise is filtered with the standard specified filter characteristic.

The SERDES reference clock phase noise contributes to the transmit output phase noise (Figure 4). Although not always the case, the CMU –3-dB bandwidth is greater than the highpass corner of the serial data measurement bandpass filter. You can determine the contribution of the reference clock phase noise to the transmitter's phase noise by applying a lowpass filter over the CMU phase-locked loop bandwidth to the clock phase noise and then a highpass filter as specified by the transmit jitter standard. Integrating the resultant phase noise curve provides an estimate of the rms jitter contributed by the reference clock phase noise at the SERDES terminals.

The SERDES receiver

The function of the receive channel of a SERDES is to recover the data and clock from the serial data without any bit errors and deserialize it to a lower-rate parallel word for use by the ASIC. The clock and data recovery (CDR) algorithm of a SERDES varies (Reference 6). There are methods that utilize the time base from the SERDES CMU as well as methods that are totally independent of the CMU time base. Two distinct uses of the CMU time base are as a frequency acquisition aid and as a time base for the generation of a phase-modulated version of the time base. The latter class of CDR includes continuous and digitally controlled phase interpolators, oversampling, and discrete phase-selection architectures.

The bit error rate performance of the class of CDR that use the CMU time base as a frequency acquisition aid is independent of the quality of the reference clock supplied to the SERDES terminals since the use of the time base as a frequency acquisition aid does not affect the data-recovery performance of the receiver. This assumes that the transition of the receiver between its frequency acquisition mode and its phase acquisition mode occurs before the target BER is achieved. However, when the clock derived from the SERDES CMU is phase-modulated by the receiver based on the serial data transitions, the quality of the CMU time base will affect its bit error rate performance.

When the receiver architecture modulates the clock from the SERDES CMU based on serial data transitions, the quality of the CMU time base will affect the bit error rate performance of the SERDES receiver. You cannot distinguish phase modulation of the CMU time base from phase modulation of the serial input data stream. Therefore, phase modulation of the CMU time base results in a decrease in receiver jitter tolerance when compared with its jitter tolerance using an ideal CMU time base. The reference clock phase noise at the SERDES input terminals appears as phase noise on the high-speed serial data at the receiver terminals (Figure 5). The phase noise of the external reference clock is lowpass-filtered by the CMU phase-locked loop. In Figure 5, the CMU phase-locked loop is shown with no jitter peaking. However, peaking may be present in its jitter transfer function, and that will add to the phase noise of the reference clock. The filtered reference clock phase noise is now part of the time base the receiver uses to recover the serial data.

You can model the data-recovery process as a lowpass-filtering operation that bandlimits the reference clock phase noise from the CMU. In this example, the –3-dB frequency of the CMU phase-locked loop is less than the –3-dB corner frequency of the CDR loop. However, the relative locations of the two –3-dB frequency corners are independent and will generally differ from that in Figure 5. Also shown is some potential jitter peaking in the CDR transfer characteristic. Since the serial input data over this frequency range will be weighted by the CDR jitter transfer function, you can expect a reduced receiver jitter tolerance over the frequency range of jitter peaking in the CDR and in the CMU phase-locked loop transfer function.

The serial data standards that govern the performance of SERDES transmitter outputs also define a minimum receiver jitter tolerance (Figure 6).

The filtered reference clock phase noise reduces the SERDES receiver sinusoidal jitter tolerance. For example, if the filtered reference clock phase noise contains deterministic jitter evident as discrete spectral tones in its phase noise, these tones will reduce the sinusoidal jitter tolerance of the receiver at the specific frequency of the tones. If the filtered reference clock phase noise is random in nature, its peak value has the ability to affect the receiver jitter tolerance at any sinusoidal frequency.

You can examine the effect of reference clock phase noise on receiver performance by comparing the peak-to-peak random jitter you computed for the filtered external reference clock phase noise with the high-frequency limit of the sinusoidal jitter tolerance requirement. You can then compute a maximum limit on the random phase noise of the external reference clock. First, compute the externally applied reference clock phase noise contribution to the receiver time base using the externally applied reference clock phase noise at the SERDES terminals, the CMU phase-locked loop transfer function, and the CDR transfer function. Then determine the frequency and magnitude of all significant tonal contributions contained in the filtered reference clock phase noise. You should remove the tonal frequency contributions of the reference clock filtered phase noise to produce a filtered phase noise characteristic devoid of significant tonal energy. Using the target bit error rate of the serial data standard of interest, the frequency range of the serial data standard sinusoidal jitter tolerance requirement, and the filtered reference clock phase noise devoid of significant tonal energy, compute the peak-to-peak random jitter due to the filtered reference clock phase noise. Determine the reduction in receiver sinusoidal jitter tolerance using the set of tonal contributions at each of the tonal frequencies and establish a potential limit on the phase noise of reference clock tonal energy at any frequencies where the jitter reduction is significant. Using the high-frequency limit of the sinusoidal jitter tolerance standard (where the sinusoidal jitter tolerance is at its minimum), compare the peak-to-peak random jitter computed for the filtered external reference clock with the requirement limit. Set a maximum limit on the external reference clock random phase noise to reduce its filtered value to an acceptable level.