News and New Products

16-bit, dual-channel ADCs span 20M to 80M samples/sec

By Paul Rako, Technical Editor -- EDN, 11/4/2009

Analog Devices’ new AD9269 family of 20M-, 40M-, 65M-, and 80M-sample/sec pipeline ADCs takes 16-bit samples. The units consume 42 to 93 mW of power, depending on speed, and they integrate both a reference and a sample-and-hold circuit. The differential-input stage features a 700-MHz bandwidth, and output data is on separate parallel interfaces for each channel. Targeting use in wireless base stations, the ADCs feature a quadrature-decoding error-correction block to improve the performance of an I/Q (in-phase/quadrature) complex signal-receiver system. They operate from a 1.8V analog supply and a 1.8 to 3.3V power supply for the output section. SNR (signal-to-noise ratio) is 77 dBFS (decibels relative to full-scale) at a 10-MHz input and 73 dBFS at a 170-MHz input frequency. The SFDR (spurious-free dynamic range) is 90 dBc (decibels referenced to the carrier) at 10 MHz and 78 dBc at 170-MHz input frequencies. The ENOB (effective number of bits) is 12.4 for inputs of 9.7 to 30.5 MHz, 12.2 for inputs at 70 MHz, and 11.6 for input frequencies of 170 MHz.

The AD9269 is available in a 9×9-mm, 64-pin LF-CSP with suggested retail prices of $49, $59.50, $73.66, and $84.09 (1000) for the 20M-, 40M-, 65M-, and 80M-sample/sec versions, respectively. They operate over a −40 to +85°C temperature range. Production quantities will become available in January 2010.