Taking power analysis to the transistor level for a full chip

GUEST OPINION: Neither functional simulation nor conventional power estimation can catch some major issues in power consumption for low-power designs. Large-area mixed-signal simulation may be the right answer.

By Bradley Geden, CustomSim, Synopsys Inc -- EDN, 12/4/2009

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize power consumption. These techniques include the usage of dc/dc converters, charge pumps, and voltage regulators, all of which are analog in nature. Recently there has been quite a bit of publicity surrounding mixed-signal design and simulation. The emphasis has been on full-chip functional verification and introducing analog concepts such as real numbers into the digital verification world. However, at the full-chip level, functional verification is only a small part of the many essential tasks performed before tapeout that can benefit from mixed-signal simulation.

Front and center in every IC designer's mind is power consumption—how to reduce it, characterize it, and then ensure power-management techniques are working. We are all well aware that almost every IC designed today is mixed-signal in nature due to the presence of regulated power supplies, PLLs (phase lock loops), and other power-optimization technologies. In addition, more of the end-user system is being incorporated onto a single die to reduce integration costs and to produce broad platforms that can be used in multiple applications. These SOC (system-on-chip) platforms have literally hundreds of modes of operation, each of which employs a complex array of power-management techniques to minimize power consumption.

Design teams need an efficient analysis solution that will enable them to ensure that power-management techniques are working correctly in all modes of operation. A single mistake in power management will render a design useless as it drains the current from a battery when it is supposed to be in standby mode. Spice-level simulations will accurately measure power consumption, but many design teams are only able to simulate a handful of operating modes before tapeout in this manner. In many cases, these simulations are still running well after the tapeout date due to aggressive tapeout schedules. Therefore, Spice-level simulations at the full-chip level, while accurate, are impractical for high-coverage power analysis.

Analyzing power consumption at the full-chip level in all modes of operation is particularly challenging. Failure mechanisms such as incorrectly connected power supplies, floating nodes, and leakage paths are not typically found at the logic level but are exhibited at the device level. This requires simulations be run almost entirely at the transistor level for accurate power analysis. These different modes of operation require different power measurements to be made, whether for dynamic, standby, or leakage power. The currents involved, especially with leakage power, are very small, and therefore, the transistor-level simulations need to be accurate. System-level verification engineers have created comprehensive testbenches in SystemVerilog/Verilog or VHDL to exercise all the different modes of operation for the SOC platform. It does not make sense to replicate this effort in the transistor domain by painfully recreating stimuli and applying these to a transistor-only simulation. A mixed-signal simulation solution that employs a high-capacity, high-performance, and accurate transistor-level simulation engine is clearly required.

Design teams today are performing dynamic full-chip power measurement and analysis on multimillion-transistor designs. Some examples include a memory channel I/O with 1.9 million transistors, a wireless SOC platform with 3 million transistors, and image sensor arrays containing more than 1 million transistors. Not only does dynamic, standby, and leakage power need to be analyzed in every mode of operation, but multiple PVT (process, voltage, and temperature) corners must be run as well.

Time and time again, we hear about designs that tapeout on time and came back from the foundry functionally correct, yet consume large amounts of power well exceeding the power budget. When these designs have been simulated at the transistor level, the causes of failure have been discovered and repaired. Therefore, full-chip power analysis is a mandatory step in the design team's sign-off flow.

Why go to all the trouble to simulate the majority of the design at the transistor level? Let us consider the alternative. If the designer chooses to introduce additional levels of abstraction for parts of the design using either real numbers in Verilog or VHDL or AMS behavioral languages, there is always the danger that blocks at different power supplies could be driving circuits that have been put into standby mode. This situation can cause the circuits in standby mode to draw excess current because the techniques used to power-down the block are not working correctly. Unwanted dc leakage paths due to floating gates are a typical failure that can be missed if the interaction between the different blocks is not modeled correctly. On the other hand, it is important to use the same SystemVerilog, Verilog, or VHDL testbenches that are used for functional verification so that all the different modes of operation are explored. This is only possible when using a mixed-signal simulation solution. The trade-off between the level of abstraction used to model the analog blocks and the coverage for the different analysis types is illustrated in Figure 1.

The challenge is finding a mixed-signal simulation solution with the capacity to simulate multimillion-transistor designs while simultaneously delivering the required accuracy for full-chip power analysis including leakage power. Mixed-signal simulation solutions on the market today use different simulation technologies for high-performance transistor-level simulation. The performance bottleneck is usually focused on the transistor-level simulation engine. Therefore, one of the key criteria for selecting a mixed-signal simulation solution is the capacity, performance, and accuracy of the transistor-level simulation engine. During evaluations, it is important to determine who has the capacity to simulate the design and deliver the required accuracy for full-chip power analysis with results that correspond to silicon.

Going beyond full-chip power analysis, designers need to ensure that the IC's power-up and power-down sequences are working correctly. Since power-management units have long time constants, these mixed-signal simulations require very long transient analysis with a large percentage of the design being modeled at the transistor level. In addition to capacity and accuracy, the mixed-signal solution must run these long transient simulations in a reasonable time so that designers can build confidence in their designs before tapeout. Timing at the analog/digital interface also needs to be analyzed to ensure that no timing violations are introduced by adding analog and custom blocks into the top-level design. Designers can use mixed-signal simulation to analyze timing for signals passing between digital and analog blocks.

What about using analog/mixed-signal languages (AMS-HDL) to speed full-chip mixed-signal simulation? While languages such as Verilog-AMS and VHDL-AMS hold a lot of promise, they are only really applicable for full-chip functional verification. They cannot be used for accurate transistor-level power analysis, power sequence analysis, and mixed-signal timing analysis because they cannot accurately model the analog circuitry and device-level effects that can cause leakage. Even for full-chip functional verification, the challenge has always been model creation and validation. Analog design engineers would need to learn to program in AMS-HDL, or digital verification engineers would need to learn more about analog functionality. Once these models are created, how should designers validate that these models match the transistor-level implementation? A compromise has been to take advantage of real number modeling, either in Verilog or VHDL, which is supported by most logic simulators today.

These are indeed exciting times for mixed-signal simulation. Full-chip functional verification is no doubt a major target for mixed-signal simulation. However, it is only one of many mixed-signal simulation tasks that must be performed at the top level to ensure designs meet specification. In addition to full-chip functional verification, designers need to run full-chip power analysis to characterize dynamic, standby, and leakage power in all modes of operation, ensure power-up and power-down sequences are working correctly, and mixed-signal timing analysis at the analog/digital boundary. These critical analyses require a mixed-signal simulation solution that has the capacity and performance to simulate designs with millions of transistors while delivering the accuracy to measure extremely small currents. With the right solution, design teams can avoid costly re-spins due to failures in power-management circuits or unexpected leakage power in standby modes. Many more simulations will be possible before tapeout, significantly increasing coverage and designer confidence and, ultimately, profitability.

Author Information

Bradley Geden is the product marketing manager for Synopsys' CustomSim circuit simulation solution. He has more than 14 years of experience in the EDA and semiconductor industries. Geden started his career as an analog/mixed-signal IC design engineer at the SAMES foundry in South Africa and subsequently joined CML Micro in the UK, where he was responsible for leading IC design teams delivering products to the wireless and wireline markets. During the last eight years, he has held product marketing and sales positions at Mentor Graphics and Synopsys. Geden received his bachelor's degree in electronic engineering from the University of Pretoria in South Africa.