Measurement techniques help hit the 1-ppm mark

Part 2 of this series on the design of a 20-bit DAC discusses the all-important techniques for testing the performance-linearity, settling time, and noise-at such minuscule data levels. See Part 3 in the next issue.

By Jim Williams, Linear Technology Corp -- EDN, 4/26/2001

A true 20-bit DAC that fits on a circuit board and costs approximately $100 to build is a design milestone (see Part 1 of this article, EDN, April 12, 2001, pg 95). Claiming to achieve this level of performance is one thing, but proving it with precise measurements is another. The measurement techniques are at times more exacting than the actual circuit's design. Part 2 of this series presents approaches and circuits for measuring linearity, settling time, and noise.

Measure linearity to 1 ppm

Of these three measurements, determining the DAC's linearity requires the greatest effort. Verifying 1-ppm linearity of the DAC and the integral ADC requires special considerations, and, interestingly, some help from the 19th century. Testing necessitates some form of voltage source that produces equal-amplitude output steps for incremental digital inputs. Additionally, for measurement confidence, it is desirable that the source be substantially more linear than the 1-ppm requirement. This demand is stringent and painfully close to the state of the art.

The most linear "digital-to-analog" converter is also one of the oldest. Lord Kelvin's KVD (Kelvin-Varley divider) is, in its most developed form, linear to 0.1 ppm. This manually switched device features 10 million individual dial settings arranged in seven decades. You can think of the device as a three-terminal potentiometer with fixed "end-to-end" resistance and a seven-decade switched wiper position (Figure 1a).

The actual construction of a 0.1-ppm KVD is more artistry and witchcraft than science. The market is relatively small, the vendors few, and the resultant price high. If $13,000 for a bunch of switches and resistors seems offensive, try building and certifying your own KVD. The KVD in Figure 1b has a 100-kW input impedance. Thus, wiper's output resistance is high and varies with setting. As such, a very low bias-current follower is necessary to unload the KVD without introducing significant error (Figure 1c). The LT1010 output buffer allows for driving cables and loads and, more subtly, maintains the amplifier's high open-loop gain.

The schematic in Figure 1c is deceptively simple. In practice, construction details are crucial. Parasitic thermocouples, or namely the Seebeck effect; layout; grounding; shielding; guarding; cable choice; and other issues affect achievable performance. Part 3 discusses these issues in detail. In fact, as good as the chopper-stabilized LTC1150 is with respect to drift, offset, bias current, and CMRR (common-mode rejection ratio), selection is necessary if you seek sub-ppm nonlinearity performance. An error-budget analysis details some of the selection criteria (Figure 2). You can test the buffer with Figure 2a's circuit. As you run the KVD through its entire range, the floating null detector must remain well within 1 ppm, or 5 µV, and preferably at less than 0.5 ppm. This test ensures that you account for all error sources, particularly I_B and CMRR, whose effects vary with operating point. Measured performance indicates that the sum of all errors called out in Figure 2b are well within desired limits.

Circuit construction is critical

The detailed schematic of the sub-ppm-linearity voltage source includes offset trim, a stable voltage source, and a second KVD to drive the main KVD (Figure 3). Additionally, an ensemble of three HP3458A voltmeters monitors the output. The offset trim bleeds a small current into the main KVD ground return, producing a few microvolts of offset-trim range. This range allows you to functionally trim out all sources of zero error, such as amplifier offsets and parasitic thermocouple mismatches, permitting a true zero-volt output when the main KVD setting is all zeros. Three voltmeters, which have a specification of less than 0.1-ppm nonlinearity on the 10V range, "vote" on the source's output. In other words, each voltmeter monitors the source's output. Then, you correct each reading for absolute error and average the three corrected readings to obtain the apparent linearity.

The single-point-grounding scheme prevents the mixing of return currents and the attendant errors. The shielded cables for connecting the KVDs and voltmeters should have low-thermal-activity specifications. Keithley type SC-93 and Guildline #SCW are suitable. Crush-type copper lugs, as opposed to soldered types, provide lower parasitic-thermocouple activity at KVD and DVM connection points. However, you must keep the lugs clean to prevent oxidation, thus avoiding excessive thermal voltages (see Part 3). A copper deoxidant (Caig Labs "Deoxit" D100L) is effective for maintaining such cleanliness. Low thermal lugs and jacks, preterminated to cables, are also available (Hewlett-Packard 11053, 11174A) and convenient.

Thermal baffles that enclose the KVD and DVM connections tend to thermally equilibrate their associated banana-jack terminals, minimizing residual parasitic-thermocouple activity. Additionally, you should restrict the number of connections in the signal path. You also need to balance electrical connections in the signal path against each other such that the net signal-path degradation due to thermocouples is nominally equal to zero. When you introduce a deliberate thermocouple, be sure to match materials. Complying with this guideline may necessitate a deliberate introduction of solder-copper junctions, marked "X" on Figure 3, to obtain optimum differential cancellation (see Part 3). Simply breaking the appropriate wire or pc trace and soldering it facilitates this cancellation. Ensure that the introduced thermocouples temperature-track the junctions they are supposed to cancel. You can usually ensure temperature tracking by locating all junctions close to each other.

The noise-filtering capacitor at the main KVD is a low-leakage type; the output buffer drives the capacitor's metal to guard against surface leakage.

When studying this measurement approach, it is essential to differentiate between linearity and absolute accuracy. This differentiation eliminates concerns with absolute standards, permitting certain freedoms in the measurement scheme. In particular, although Figure 3 uses single-point grounding, the circuit does not use remote sensing. This choice is deliberate, made to minimize the number of potential error-causing parasitic thermocouples in the signal path. Similarly, the design does not use a ratiometric reference connection between the KVD LTZ1000A voltage source and the voltmeters for the same reason. In theory, a ratiometric connection affords lower drift. In practice, the resultant introduced parasitic thermocouples obviate the desired advantage. Additionally, the aggregate stability of the LTZ1000A reference and the voltmeter references (also, incidentally, LTZ1000A based) is comfortably inside 0.1 ppm for periods of 10 minutes, which is more than enough time for a 10-point linearity measurement.

Figure 4 and Figure 5 are photographs of the voltage source and the reference-buffer-box internal construction. This KVD-based, high-linearity voltage source has been in use for years. The measurement regime involves three steps:

• verifying KVD linearity by intercomparison with other KVDs and by an independent calibration laboratory,
• taking worst-case voltmeter ensemble deviations over 0 to 5V every 0.5V, and
• performing 100 runs (10 per day, once per hour).

During this period, the total linearity uncertainty defined by the source and its monitoring voltmeters is just 0.3 ppm. This value is more than three times better than the desired 1-ppm performance, promoting confidence in your measurements. A delightful activity, particularly for those wholly unenthralled with Web surfing, is to spend hours "surfing the Kelvin." This activity consists of dialing various KVD settings and noting ADC agreement within 1 ppm. This astonishingly nerdy behavior thrills certain types.

Measuring DAC settling time

Measuring the 20-bit DAC's output settling time is a challenging task. Although the time scale involved is relatively slow, the LSB step size of 5-µV presents problems. The issue reduces to obtaining a great deal of gain without inducing overdrive in the monitoring oscilloscope. Such overdrive will corrupt the measurement, rendering displayed results meaningless.

The input structure of Figure 6 resistively balances the DAC output against the precision variable reference supply, such as in Figure 3, which is adjustable in 0.5-µV steps. The circuit's remainder constitutes a clamped, distributed gain-of-2000 amplifier. Diode clamping at each gain-stage input prevents saturation from occurring even with large DAC-reference supply imbalances. The distributed gain allows a 10-kHz bandwidth while maintaining clamping effectiveness. The monitoring oscilloscope, operating at 5 or 10 mV/DIV (5 to 10 µV at the DAC output) can readily discern 5-µV settling without incurring deleterious overdrive.

Layout and construction of this circuit requires care. A linear layout minimizes parasitic feedback paths, preventing oscillation (Figure 7). The construction fully shields the DAC input-step signal, preventing feedthrough to various sensitive points within the amplifier. Finally, the entire circuit sits in a shielded enclosure to minimize effects of stray RF and pickup.

You can test the settling-time test circuit by applying a test step that settles much faster than the DAC. One method is to use a mercury-wetted reed-relay-based pulse generator to supply the step (Figure 8a). The mercury-wetted reed relay opens in 5 nsec, and the when the relay opens, the circuit's output settles essentially instantaneously relative to DAC speed and settling-time-amplifier bandwidth. The relay in Figure 8a is commercially available, but you can obtain similar results with standard mercury-based reed relays. You test Figure 6's response by grounding one input and driving the other input with Figure 8a's pulse generator. The test circuit settles to within 1 ppm (±5 µV) in 2 msec (Figure 8b). This time is much faster than the DAC's settling time, lending confidence to the settling-time results of Part 1.

Measuring microvolt noise levels

Verifying DAC output noise requires a quiet, high-gain amplifier at the oscilloscope. Figure 9a shows one way to take the measurement. The input preamplifier, operating at a gain of 1000, has a highpass cutoff at 0.1 Hz and drives the oscilloscope via a 10-Hz discrete lowpass filter. The oscilloscope, set to 1 mV/DIV, indicates 1 µV/DIV referred to the preamplifier input. Figure 9b indicates that the DAC output noise is well below an LSB, about 0.9 µV. Equipment limitations set the measurement noise floor at 0.2 µV. These signal levels dictate a completely shielded, coaxial path from breadboard to oscilloscope (Figure 10).

Table 1 lists some applicable high-sensitivity amplifiers suitable for the noise measurement. Current-generation oscilloscopes rarely have sensitivities greater than 2 mV/DIV, although older instruments offer more capability. The table lists representative preamplifiers and oscilloscope plug-ins suitable for noise measurement. These units feature wideband, low-noise performance. It is particularly significant that many of these instruments are no longer in production. This fact is in keeping with current instrumentation trends, which emphasize digital-signal acquisition as opposed to analog-measurement capability.

The monitoring oscilloscope should have exceptional trace clarity. In the latter, high-quality analog oscilloscopes are unmatched. The exceptionally small spot size of these instruments suits low-level noise measurement. Tektronix types 453, 453A, 454, 454A, 547, and 556 are excellent choices. Their pristine trace presentation is ideal for discerning small signals of interest against a noise-floor-limited background. The digitizing uncertainties and raster-scan limitations of DSOs impose display-resolution penalties. Many DSO displays will not even register the fine structure of the noise waveform.

Author info

Jim Williams is a staff scientist at Linear Technology Corp (Milpitas, CA, http://www.linear-tech.com), where he specializes in analog-circuit and instrumentation design. He has served in similar capacities at National Semiconductor, Arthur D Little, and the Instrumentation Laboratory at the Massachusetts Institute of Technology (Cambridge, MA) where he first encountered serious 1-ppm measurement using the KVD. A former student at Wayne State University (Detroit), Williams enjoys art, collecting antique scientific instruments, and restoring old Tektronix oscilloscopes.

ACKNOWLEDGMENTS

I am indebted to Lord Kelvin and to Warren Little of the CS Draper Laboratory (née Massachusetts Institute of Technology Instrumentation Laboratory) standards lab. Warren taught me, with great patience, the wonders of KVDs some 30 years ago, and I am still trading on his efforts.