Feature

Simulating mixed-mode designs with Verilog-only models

PLL circuits offer developers of mixed-signal designs a unique challenge. Commonly used as frequency synthesizers, clock multipliers, or clock-recovery devices, PLLs are crucial to many microcontrollers and microprocessors. As more functions enter the digital domain, verification becomes more difficult and requires more sophisticated models. A Verilog-only model can solve most of these problems.

Anis Jarrar, Kelvin McCollough, Jim Caserta, Motorola -- EDN, 1/4/2001

As the capacities of today's chips grow and their geometries shrink, specialized clock-generation circuits are necessary to reduce electrical-magnetic emissions. One scheme that is gaining industry acceptance is frequency modulation of the system clock. Validating such systems has been notoriously difficult in the past, primarily because of the extended simulation times that validating required. As a result, high-level models became a necessity for design validation. Engineers usually developed such models in C; Fortran; or a commercial mathematical tool, such as Matlab. Yet, modern simulators and computing resources have become advanced enough to allow transistor-level verification of PLLs. Recently, designers have used tools, such as Synopsys' PowerMill ACE (Analog Circuit Engine), to verify the PLLs at the transistor level. PowerMill ACE was used to verify the first generation of FM-PLLs on earlier microcontroller chip designs.

Validating the second generation of FM-PLLs requires a different strategy, because most of the new development is in the digital control logic. Designers developed and implemented a calibration algorithm to trim the magnitude of the change in frequency superimposed on the system clock. The calibration is necessary to overcome the limitations that the baseline process and the large variation in the analog building blocks impose. Designers can resolve the final change in frequency to within 2% of the system frequency with a maximum 2% error. The calibration sequence requires approximately 1 msec in real time. Prior to adding the calibration, the PLL achieved frequency lock in approximately 200 msec in real time. Therefore, the total required real-time simulation is approximately 1.2 msec, and consequently, the verification emphasis shifts from analog to digital.

In response to this strategy, designers developed a Verilog-only model, allowing the rapid and extensive verification of the new calibration algorithm. Although the ACE option is still valid, its simulation time is prohibitive. Using a Verilog/VerilogA model is another option, but models are not fully developed. Moreover, fully developed VerilogA models could increase the simulation times to the point at which using the ACE becomes a better option. This situation is especially true when you consider that you need not develop special models to support ACE. VerilogA is a good tool for architecture trade-off analysis and for conducting what-if scenarios at the beginning phases of the design process.

The PLL design

FM-PLLs use a reference of 2 to 20 MHz to produce an output range of 80 to 160 MHz. The system that incorporates this PLL operates at one-quarter of the FM-PLL's output-clock frequency. The frequency modulation targets a 100- or 200-kHz rate and a depth of 2, 4, or 6% of the system frequency (Figure 1).

The digital portion of the PLL is synthesized. Its functions include a feedback divider, lock detection, a center-frequency search algorithm, and a frequency-modulation algorithm. The digital block uses about 2165 cells. The total RTL (register-transfer-level) count reaches 1669 lines. The nominal power-supply voltage is 3.3V, and the targeted power consumption is less than 2 mA for the total analog circuitry. The designers used a CDR1 (Communications Design Rules) baseline process of 0.35-mm Leff, 90A oxide threshold voltages targeting a 600-mV, single-polysilicon, triple-metal CMOS process. The PLL comprises a phase-frequency detector, charge pumps, two RC loop filters, main and reference ICOs (current-controlled oscillators), a current-reference generator, a voltage reference, a frequency-to-current converter, current D/A converters, divider blocks Q and P, center current SAR (successive approximation register), calibration control, a calibration shift register, and loss-of-lock and loss-of-clock detection (Figure 2).

The FM-PLL Verilog model

The BLM (behavioral-level model) of an FM-PLL aims to provide an accurate model of all the analog blocks within the module, enabling you to verify the increasingly complex digital section using a standard logic simulator, such as Verilog-XL. The BLM maintains the existing design hierarchy, reuses all of the RTL code for the digital blocks without modification, and keeps the I/O list for each module the same as the real model. Several challenges arise in creating an accurate BLM; most are due to Verilog's inherent inability to model and simulate currents and voltages.

To overcome these obstacles, you should create a virtual high-frequency clock to perform discrete time simulation. The simulator treats all voltage and current values as real Verilog variables and samples and updates their values on the positive edge of the virtual clock. The clock provides the necessary time increment (Dt) to update the critical currents and voltages within the analog circuits that allow the BLM to accurately model the real circuit. The virtual clock for this simulation has a frequency of 2.5 GHz and provides the simulator a time increment of 400 psec. This value depends on the bandwidth of the analog components you are modeling and the resolution that the simulation requires. Take care in selecting this frequency; arbitrarily increasing it will negatively impact the overall simulation time.

A method for passing current and voltage values between the blocks is necessary to complete the BLM. One possible method is to convert these values into vectored signals between the various modules. However, because the I/O list for each block must remain the same to eliminate the need for a separate simulation database, this method is inadvisable. Instead, you should use hierarchical variable references and global defines to achieve the required block connectivity.

This model generates a frequency-modulated clock that can interact with and that you can simulate with the rest of the digital logic in the module without a computation-intensive mixed-mode simulator. To ease the reuse of this module, designers created a Verilog-environment file that defines all critical circuit parameters (some of which you obtain through traditional Spice simulations). This file is included with the rest of the Verilog design files, and you can change it at the beginning of every simulation to explore design trade-offs. Listing 1 contains an excerpt from this file.

Blocks modeled in Verilog

The relationship between the current and the frequency in the main oscillator is linear. The product of the ICO gain and the current that is supplied to the oscillator determine the frequency. This assumption is a simplified approximation of the ICO operation, because frequency shifts in this model occur instantly in response to input current changes. Once you know the ICO frequency, you can synthesize the system clock by defining the clock high and low times. Figure 3 illustrates how you can perform this calculation in Verilog.

The I_P charge-pump loop filter is modeled as an integration capacitor (C_INT ) connected to a unity gain buffer whose output connects to a filter resistor (Figure 4). The current entering the ICO from the filter is modeled in Verilog (Listing 2). The I_R charge-pump loop filter is modeled similarly to the I_P loop filter as a simple RC circuit (Figure 5). The current entering the ICO from the filter is modeled in Verilog as shown in Listing 3.

The PFD (phase-frequency detector) is a custom digital circuit that generates the up-and-down control signals to the charge pumps. These signals control the polarity of the charge pumps' output currents. Listing 4 shows both the PFD and charge-pump models.

The frequency-to-current circuit generates the necessary current to perform the frequency dithering of the main ICO output clock. It uses a 2-bit signal to control the modulation depth. The output current is proportional to the input frequency and reference voltage. An 8-bit DAC converter supplies this reference voltage. The Verilog code in Listing 5 implements the function described above.

The simulation testbench integrates the analog BLM and the digital control blocks into the microcontroller and simulates them in the full-chip Verilog environment. Verification engineers write nine patterns to test the FM-PLL digital block. Engineers also run 30 legacy patterns to verify basic PLL functions. The patterns verify the digital-control RTL and the gate netlist. Initially, verification engineers created vcd (value-change-dump) files so that designers could examine the simulation output to verify proper BLM operation and basic calibration functions. All patterns generate log files detailing the pass/fail status of each operation. A typical pattern contains the following steps:

1. Enter PLL Mode; wait for PLL to lock. Using the vcd file, you can observe the frequency of the output clock and compare it with the expected behavior. Figure 6 shows the ICO clock frequency and lock status bit.

2. Check lock-bit status. The lock bit is set only when Ffdbk=Fref, thus you can measure the frequency and time at which the lock bit is set. You determine the frequency at which the PLL locks using the vcd file and verify the lock-bit status with the pattern.

3. Program modulation by writing to specific memory locations. This action initiates the calibration sequence.

4. Observe calibration routine. The ICO clock in the BLM is modulated to provide the stimulus for the digital control block. You can observe intermediate digital values by the pattern for each iteration of the calibration routine, including the measured frequency count, the frequency offset count, the difference between actual offset and target offset, the calibration DAC code, and a calibration-status bit. The analog effects you observe in the vcd file are the change in ICO frequency, the frequency-to-current output current, the modulation DAC output current, and the calibration DAC output voltage (Figure 7 and Figure 8).

5. Wait for calibration routine to end. The pattern checks the calibration completion flag.

6. Wait for PLL to relock . You observe the frequency shift in the vcd file as the loop closes again. You measure the change in frequency from the vcd file after the calibration routine finishes. The pattern reads the final calibration settings.

Verification patterns are developed for many purposes; general patterns observe operation for different register settings (multiplication factor, or divP; modulation depth; or modulation rate). You can model a process shift by modifying the environment file, thus introducing errors into the BLM. You can also model voltage or temperature shifts in a similar fashion to produce errors in the model. Running a general pattern allows you to observe the calibration routine and see how it trims out the error by adjusting analog values in the BLM and thus produces the desired change in frequency. Aligned and unaligned patterns verify proper operation of the control block's arithmetic logic unit. Calibration-self-check patterns verify the proper operation of the calibration-status bit. The patterns check that the bit is set while calibration is enabled, unless the pattern induces a failure. When a failure is induced or calibration is disabled, you should clear the calibration-status bit. Overflowing the counters by generating a clock frequency greater than the PLL specification is one way to induce failure. Make control-register changes at different stages of the algorithm to observe proper state-machine operation.

A lock, calibration, and relock sequence runs in 30 minutes. For RTL debugging, this length of time is a limiting factor. For debugging the gate-level netlist and timing, you should perform synthesis and place and route after all RTL code or constraint changes. This process takes approximately four hours. Designers completed the RTL and timing analysis of the FM-PLL design in six weeks, allowing timely delivery. By comparison, a concatenation of one lock, calibration, and re-lock sequence running in ACE takes five days to complete. Thus, the design team was able to achieve a 240X reduction in simulation time. The designers perform all simulations on Ultra30 Sun workstations (300 MHz with 1024 Mbytes of RAM). The number of RTL code iterations needed for the digital-control-logic debugging would be impossible if the designers used ACE as the verification tool. Using a compiled Verilog simulator instead of an interpretive simulator (Verilog-XL) reduces the time by a factor of five, bringing simulation time to less than 5 minutes.

The BLM highlights inadequacies that occur when you use unit delays for gate-level simulation. In the BLM, the ICO generates a frequency of 60 MHz, which feeds a post divider. This divider, which is characterized in silicon, can handle signals greater than 100 MHz; however, the gate model is stuck at 0 for any frequency greater than 60 MHz.

Using a Verilog simulation environment dramatically increases the number of people who can verify the module. The model allows insight into analog functioning using a pure digital simulator. Test engineers port these PLL verification patterns to the Teradyne J971 tester, and manufacturing uses them in production. Testing the calibration routine in production increases the level of testing of the analog circuits.

BLMs allow the FM-PLLs to improve their accuracy by adding digital functions. Processing, voltage, and temperature variations limit the accuracy of the analog circuitry. BLMs allow rapid and extensive test coverage and let the digital-verification team assist in verifying mixed-signal modules. You can measure the benefits of BLMs and verification in your ability to meet mask-shop deadlines and achieve first-pass silicon functioning within specification.